Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3166ba04 authored by Shawn Lin's avatar Shawn Lin Committed by Bjorn Helgaas
Browse files

PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu() 



Configuration accesses is also part of ATU settings, so let's keep all of
them inside rockchip_pcie_cfg_atu().

Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 7a1d3b8c

drivers/pci/host/pcie-rockchip.c

+11 −10
Original line number Diff line number Diff line
@@ -664,16 +664,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 
		rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);

	}



	rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);



	rockchip_pcie_write(rockchip,

			    (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),

			    PCIE_CORE_OB_REGION_ADDR0);

	rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,

			    PCIE_CORE_OB_REGION_ADDR1);

	rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);

	rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);



	return 0;

}
@@ -1163,6 +1153,17 @@ static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip) 
	int err;

	int reg_no;



	/* Configuration Accesses for region 0 */

	rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);



	rockchip_pcie_write(rockchip,

			    (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),

			    PCIE_CORE_OB_REGION_ADDR0);

	rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,

			    PCIE_CORE_OB_REGION_ADDR1);

	rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);

	rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);



	for (reg_no = 0; reg_no < (rockchip->mem_size >> 20); reg_no++) {

		err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,

						AXI_WRAPPER_MEM_WRITE,