Loading drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c +40 −8 Original line number Original line Diff line number Diff line Loading @@ -162,6 +162,34 @@ static void __cam_req_mgr_dec_idx(int32_t *val, int32_t step, int32_t max_val) *val = max_val + (*val); *val = max_val + (*val); } } /** * __cam_req_mgr_validate_inject_delay() * * @brief : Check if any pd device is introducing inject delay * @tbl : cam_req_mgr_req_tbl * @curr_idx : slot idx * * @return : 0 for success, negative for failure */ static int __cam_req_mgr_validate_inject_delay( struct cam_req_mgr_req_tbl *tbl, int32_t curr_idx) { struct cam_req_mgr_tbl_slot *slot = NULL; while (tbl) { slot = &tbl->slot[curr_idx]; if (slot->inject_delay > 0) { slot->inject_delay--; return -EAGAIN; } __cam_req_mgr_dec_idx(&curr_idx, tbl->pd_delta, tbl->num_slots); tbl = tbl->next; } return 0; } /** /** * __cam_req_mgr_traverse() * __cam_req_mgr_traverse() * * Loading Loading @@ -201,15 +229,18 @@ static int __cam_req_mgr_traverse(struct cam_req_mgr_traverse *traverse_data) tbl->skip_traverse, traverse_data->in_q->slot[curr_idx].status, tbl->skip_traverse, traverse_data->in_q->slot[curr_idx].status, traverse_data->in_q->slot[curr_idx].skip_idx); traverse_data->in_q->slot[curr_idx].skip_idx); if ((slot->inject_delay > 0) && if ((traverse_data->self_link == true) && (traverse_data->self_link == true)) { (!traverse_data->inject_delay_chk)) { rc = __cam_req_mgr_validate_inject_delay(tbl, curr_idx); if (rc) { CAM_DBG(CAM_CRM, "Injecting Delay of one frame"); CAM_DBG(CAM_CRM, "Injecting Delay of one frame"); apply_data[tbl->pd].req_id = -1; apply_data[tbl->pd].req_id = -1; slot->inject_delay--; /* This pd tbl not ready to proceed with asked idx */ /* This pd table is not ready to proceed with asked idx */ SET_FAILURE_BIT(traverse_data->result, tbl->pd); SET_FAILURE_BIT(traverse_data->result, tbl->pd); return -EAGAIN; return -EAGAIN; } } traverse_data->inject_delay_chk = true; } /* Check if req is ready or in skip mode or pd tbl is in skip mode */ /* Check if req is ready or in skip mode or pd tbl is in skip mode */ if (tbl->slot[curr_idx].state == CRM_REQ_STATE_READY || if (tbl->slot[curr_idx].state == CRM_REQ_STATE_READY || Loading Loading @@ -519,6 +550,7 @@ static int __cam_req_mgr_check_link_is_ready(struct cam_req_mgr_core_link *link, traverse_data.result = 0; traverse_data.result = 0; traverse_data.validate_only = validate_only; traverse_data.validate_only = validate_only; traverse_data.self_link = self_link; traverse_data.self_link = self_link; traverse_data.inject_delay_chk = false; traverse_data.open_req_cnt = link->open_req_cnt; traverse_data.open_req_cnt = link->open_req_cnt; /* /* * Traverse through all pd tables, if result is success, * Traverse through all pd tables, if result is success, Loading drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h +12 −10 Original line number Original line Diff line number Diff line Loading @@ -132,8 +132,9 @@ enum cam_req_mgr_link_state { * @apply_data : pointer which various tables will update during traverse * @apply_data : pointer which various tables will update during traverse * @in_q : input request queue pointer * @in_q : input request queue pointer * @validate_only : Whether to validate only and/or update settings * @validate_only : Whether to validate only and/or update settings * @self_link : To indicate whether the check is for the given link or the * @self_link : To indicate whether the check is for the given link or * other sync link * the other sync link * @inject_delay_chk : if inject delay has been validated for all pd devices * @open_req_cnt : Count of open requests yet to be serviced in the kernel. * @open_req_cnt : Count of open requests yet to be serviced in the kernel. */ */ struct cam_req_mgr_traverse { struct cam_req_mgr_traverse { Loading @@ -144,6 +145,7 @@ struct cam_req_mgr_traverse { struct cam_req_mgr_req_queue *in_q; struct cam_req_mgr_req_queue *in_q; bool validate_only; bool validate_only; bool self_link; bool self_link; bool inject_delay_chk; int32_t open_req_cnt; int32_t open_req_cnt; }; }; Loading Loading
drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c +40 −8 Original line number Original line Diff line number Diff line Loading @@ -162,6 +162,34 @@ static void __cam_req_mgr_dec_idx(int32_t *val, int32_t step, int32_t max_val) *val = max_val + (*val); *val = max_val + (*val); } } /** * __cam_req_mgr_validate_inject_delay() * * @brief : Check if any pd device is introducing inject delay * @tbl : cam_req_mgr_req_tbl * @curr_idx : slot idx * * @return : 0 for success, negative for failure */ static int __cam_req_mgr_validate_inject_delay( struct cam_req_mgr_req_tbl *tbl, int32_t curr_idx) { struct cam_req_mgr_tbl_slot *slot = NULL; while (tbl) { slot = &tbl->slot[curr_idx]; if (slot->inject_delay > 0) { slot->inject_delay--; return -EAGAIN; } __cam_req_mgr_dec_idx(&curr_idx, tbl->pd_delta, tbl->num_slots); tbl = tbl->next; } return 0; } /** /** * __cam_req_mgr_traverse() * __cam_req_mgr_traverse() * * Loading Loading @@ -201,15 +229,18 @@ static int __cam_req_mgr_traverse(struct cam_req_mgr_traverse *traverse_data) tbl->skip_traverse, traverse_data->in_q->slot[curr_idx].status, tbl->skip_traverse, traverse_data->in_q->slot[curr_idx].status, traverse_data->in_q->slot[curr_idx].skip_idx); traverse_data->in_q->slot[curr_idx].skip_idx); if ((slot->inject_delay > 0) && if ((traverse_data->self_link == true) && (traverse_data->self_link == true)) { (!traverse_data->inject_delay_chk)) { rc = __cam_req_mgr_validate_inject_delay(tbl, curr_idx); if (rc) { CAM_DBG(CAM_CRM, "Injecting Delay of one frame"); CAM_DBG(CAM_CRM, "Injecting Delay of one frame"); apply_data[tbl->pd].req_id = -1; apply_data[tbl->pd].req_id = -1; slot->inject_delay--; /* This pd tbl not ready to proceed with asked idx */ /* This pd table is not ready to proceed with asked idx */ SET_FAILURE_BIT(traverse_data->result, tbl->pd); SET_FAILURE_BIT(traverse_data->result, tbl->pd); return -EAGAIN; return -EAGAIN; } } traverse_data->inject_delay_chk = true; } /* Check if req is ready or in skip mode or pd tbl is in skip mode */ /* Check if req is ready or in skip mode or pd tbl is in skip mode */ if (tbl->slot[curr_idx].state == CRM_REQ_STATE_READY || if (tbl->slot[curr_idx].state == CRM_REQ_STATE_READY || Loading Loading @@ -519,6 +550,7 @@ static int __cam_req_mgr_check_link_is_ready(struct cam_req_mgr_core_link *link, traverse_data.result = 0; traverse_data.result = 0; traverse_data.validate_only = validate_only; traverse_data.validate_only = validate_only; traverse_data.self_link = self_link; traverse_data.self_link = self_link; traverse_data.inject_delay_chk = false; traverse_data.open_req_cnt = link->open_req_cnt; traverse_data.open_req_cnt = link->open_req_cnt; /* /* * Traverse through all pd tables, if result is success, * Traverse through all pd tables, if result is success, Loading
drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h +12 −10 Original line number Original line Diff line number Diff line Loading @@ -132,8 +132,9 @@ enum cam_req_mgr_link_state { * @apply_data : pointer which various tables will update during traverse * @apply_data : pointer which various tables will update during traverse * @in_q : input request queue pointer * @in_q : input request queue pointer * @validate_only : Whether to validate only and/or update settings * @validate_only : Whether to validate only and/or update settings * @self_link : To indicate whether the check is for the given link or the * @self_link : To indicate whether the check is for the given link or * other sync link * the other sync link * @inject_delay_chk : if inject delay has been validated for all pd devices * @open_req_cnt : Count of open requests yet to be serviced in the kernel. * @open_req_cnt : Count of open requests yet to be serviced in the kernel. */ */ struct cam_req_mgr_traverse { struct cam_req_mgr_traverse { Loading @@ -144,6 +145,7 @@ struct cam_req_mgr_traverse { struct cam_req_mgr_req_queue *in_q; struct cam_req_mgr_req_queue *in_q; bool validate_only; bool validate_only; bool self_link; bool self_link; bool inject_delay_chk; int32_t open_req_cnt; int32_t open_req_cnt; }; }; Loading