Merge "ARM: dts: msm: Fix clock entries for SDE on SDM855" into msm-4.14

			<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;

		clock-names = "gcc_iface", "gcc_bus",

				"iface_clk", "core_clk", "vsync_clk";

		clock-rate = <0 0 0 0 300000000 19200000 0>;

		clock-max-rate = <0 0 0 0 412500000 19200000 0>;

		clock-rate = <0 0 0 300000000 19200000>;

		clock-max-rate = <0 0 0 460000000 19200000>;

		sde-vdd-supply = <&mdss_core_gdsc>;