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Commit 30d90ade authored by Shefali Jain's avatar Shefali Jain
Browse files

ARM: dts: msm: Update clock name for OPP handle for QCS405 



Update the opp clock name for gpu device, while at it also
update the clock id for source and branch clock for GFX3D
clock to register parent clock before the branch clock.

Change-Id: Ib8322d667ae0a7f0d7a3ef3164b3c716190d9203
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent 24af5c26

arch/arm64/boot/dts/qcom/qcs405.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -309,7 +309,7 @@ 
		reg-names = "cc_base";

		vdd_cx-supply = <&pms405_s1_level>;

		clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>;

		qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>;

		qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>;

		clock-names = "cxo";

		#clock-cells = <1>;

		#reset-cells = <1>;

include/dt-bindings/clock/qcom,gcc-qcs405.h

+2 −2
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ 
#define GCC_MDSS_PCLK0_CLK				73

#define GCC_MDSS_VSYNC_CLK				74

#define GCC_OXILI_AHB_CLK				75

#define GCC_OXILI_GFX3D_CLK				76

#define GFX3D_CLK_SRC					76

#define GCC_PCIE_0_AUX_CLK				77

#define GCC_PCIE_0_CFG_AHB_CLK				78

#define GCC_PCIE_0_MSTR_AXI_CLK				79
@@ -120,7 +120,7 @@ 
#define GCC_USB3_PHY_PIPE_CLK				103

#define GCC_USB_HS_PHY_CFG_AHB_CLK			104

#define GCC_USB_HS_SYSTEM_CLK				105

#define GFX3D_CLK_SRC					106

#define GCC_OXILI_GFX3D_CLK				106

#define GP1_CLK_SRC					107

#define GP2_CLK_SRC					108

#define GP3_CLK_SRC					109