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Commit 302a5c4b authored by Ralf Baechle's avatar Ralf Baechle Committed by Jeff Garzik
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[PATCH] sgiseeq: Configure PIO and DMA timing requests. 



Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>

 drivers/net/sgiseeq.c       |   28 ++++++++++++++--------------
 include/asm-mips/sgi/hpc3.h |   40 ++++++++++++++++++++--------------------
 2 files changed, 34 insertions(+), 34 deletions(-)
Signed-off-by: default avatarJeff Garzik <jgarzik@pobox.com>
parent 2891439e

drivers/net/sgiseeq.c

+14 −14
Original line number Original line Diff line number Diff line
@@ -32,8 +32,6 @@ 




#include "sgiseeq.h"

#include "sgiseeq.h"





static char *version = "sgiseeq.c: David S. Miller (dm@engr.sgi.com)\n";



static char *sgiseeqstr = "SGI Seeq8003";

static char *sgiseeqstr = "SGI Seeq8003";





/*

/*
@@ -113,9 +111,9 @@ static struct net_device *root_sgiseeq_dev; 




static inline void hpc3_eth_reset(struct hpc3_ethregs *hregs)

static inline void hpc3_eth_reset(struct hpc3_ethregs *hregs)

{

{

	hregs->rx_reset = HPC3_ERXRST_CRESET | HPC3_ERXRST_CLRIRQ;

	hregs->reset = HPC3_ERST_CRESET | HPC3_ERST_CLRIRQ;

	udelay(20);

	udelay(20);

	hregs->rx_reset = 0;

	hregs->reset = 0;

}

}





static inline void reset_hpc3_and_seeq(struct hpc3_ethregs *hregs,

static inline void reset_hpc3_and_seeq(struct hpc3_ethregs *hregs,
@@ -252,7 +250,6 @@ void sgiseeq_dump_rings(void) 




#define TSTAT_INIT_SEEQ (SEEQ_TCMD_IPT|SEEQ_TCMD_I16|SEEQ_TCMD_IC|SEEQ_TCMD_IUF)

#define TSTAT_INIT_SEEQ (SEEQ_TCMD_IPT|SEEQ_TCMD_I16|SEEQ_TCMD_IC|SEEQ_TCMD_IUF)

#define TSTAT_INIT_EDLC ((TSTAT_INIT_SEEQ) | SEEQ_TCMD_RB2)

#define TSTAT_INIT_EDLC ((TSTAT_INIT_SEEQ) | SEEQ_TCMD_RB2)

#define RDMACFG_INIT    (HPC3_ERXDCFG_FRXDC | HPC3_ERXDCFG_FEOP | HPC3_ERXDCFG_FIRQ)





static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp,

static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp,

		     struct sgiseeq_regs *sregs)

		     struct sgiseeq_regs *sregs)
@@ -274,8 +271,6 @@ static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp, 
		sregs->tstat = TSTAT_INIT_SEEQ;

		sregs->tstat = TSTAT_INIT_SEEQ;

	}

	}





	hregs->rx_dconfig |= RDMACFG_INIT;



	hregs->rx_ndptr = CPHYSADDR(sp->rx_desc);

	hregs->rx_ndptr = CPHYSADDR(sp->rx_desc);

	hregs->tx_ndptr = CPHYSADDR(sp->tx_desc);

	hregs->tx_ndptr = CPHYSADDR(sp->tx_desc);
@@ -446,7 +441,7 @@ static irqreturn_t sgiseeq_interrupt(int irq, void *dev_id, struct pt_regs *regs 
	spin_lock(&sp->tx_lock);

	spin_lock(&sp->tx_lock);





	/* Ack the IRQ and set software state. */

	/* Ack the IRQ and set software state. */

	hregs->rx_reset = HPC3_ERXRST_CLRIRQ;

	hregs->reset = HPC3_ERST_CLRIRQ;





	/* Always check for received packets. */

	/* Always check for received packets. */

	sgiseeq_rx(dev, sp, hregs, sregs);

	sgiseeq_rx(dev, sp, hregs, sregs);
@@ -646,7 +641,7 @@ static inline void setup_rx_ring(struct sgiseeq_rx_desc *buf, int nbufs) 




#define ALIGNED(x)  ((((unsigned long)(x)) + 0xf) & ~(0xf))

#define ALIGNED(x)  ((((unsigned long)(x)) + 0xf) & ~(0xf))





static int sgiseeq_init(struct hpc3_regs* regs, int irq)

static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq)

{

{

	struct sgiseeq_init_block *sr;

	struct sgiseeq_init_block *sr;

	struct sgiseeq_private *sp;

	struct sgiseeq_private *sp;
@@ -682,8 +677,8 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq) 
	gpriv = sp;

	gpriv = sp;

	gdev = dev;

	gdev = dev;

#endif

#endif

	sp->sregs = (struct sgiseeq_regs *) &hpc3c0->eth_ext[0];

	sp->sregs = (struct sgiseeq_regs *) &hpcregs->eth_ext[0];

	sp->hregs = &hpc3c0->ethregs;

	sp->hregs = &hpcregs->ethregs;

	sp->name = sgiseeqstr;

	sp->name = sgiseeqstr;

	sp->mode = SEEQ_RCMD_RBCAST;

	sp->mode = SEEQ_RCMD_RBCAST;
@@ -700,6 +695,11 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq) 
	setup_rx_ring(sp->rx_desc, SEEQ_RX_BUFFERS);

	setup_rx_ring(sp->rx_desc, SEEQ_RX_BUFFERS);

	setup_tx_ring(sp->tx_desc, SEEQ_TX_BUFFERS);

	setup_tx_ring(sp->tx_desc, SEEQ_TX_BUFFERS);





	/* Setup PIO and DMA transfer timing */

	sp->hregs->pconfig = 0x161;

	sp->hregs->dconfig = HPC3_EDCFG_FIRQ | HPC3_EDCFG_FEOP |

			     HPC3_EDCFG_FRXDC | HPC3_EDCFG_PTO | 0x026;



	/* Reset the chip. */

	/* Reset the chip. */

	hpc3_eth_reset(sp->hregs);

	hpc3_eth_reset(sp->hregs);
@@ -726,7 +726,7 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq) 
		goto err_out_free_page;

		goto err_out_free_page;

	}

	}





	printk(KERN_INFO "%s: SGI Seeq8003 ", dev->name);

	printk(KERN_INFO "%s: %s ", dev->name, sgiseeqstr);

	for (i = 0; i < 6; i++)

	for (i = 0; i < 6; i++)

		printk("%2.2x%c", dev->dev_addr[i], i == 5 ? '\n' : ':');

		printk("%2.2x%c", dev->dev_addr[i], i == 5 ? '\n' : ':');
@@ -746,8 +746,6 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq) 




static int __init sgiseeq_probe(void)

static int __init sgiseeq_probe(void)

{

{

	printk(version);



	/* On board adapter on 1st HPC is always present */

	/* On board adapter on 1st HPC is always present */

	return sgiseeq_init(hpc3c0, SGI_ENET_IRQ);

	return sgiseeq_init(hpc3c0, SGI_ENET_IRQ);

}

}
@@ -769,4 +767,6 @@ static void __exit sgiseeq_exit(void) 
module_init(sgiseeq_probe);

module_init(sgiseeq_probe);

module_exit(sgiseeq_exit);

module_exit(sgiseeq_exit);





MODULE_DESCRIPTION("SGI Seeq 8003 driver");

MODULE_AUTHOR("Linux/MIPS Mailing List <linux-mips@linux-mips.org>");

MODULE_LICENSE("GPL");
 
MODULE_LICENSE("GPL");

include/asm-mips/sgi/hpc3.h

+20 −20
Original line number Original line Diff line number Diff line
@@ -128,26 +128,26 @@ struct hpc3_ethregs { 
	volatile u32 rx_gfptr;	/* current GIO fifo ptr */

	volatile u32 rx_gfptr;	/* current GIO fifo ptr */

	volatile u32 rx_dfptr;	/* current device fifo ptr */

	volatile u32 rx_dfptr;	/* current device fifo ptr */

	u32 _unused1;		/* padding */

	u32 _unused1;		/* padding */

	volatile u32 rx_reset;	/* reset register */

	volatile u32 reset;	/* reset register */

#define HPC3_ERXRST_CRESET 0x1	/* Reset dma channel and external controller */

#define HPC3_ERST_CRESET 0x1	/* Reset dma channel and external controller */

#define HPC3_ERXRST_CLRIRQ 0x2	/* Clear channel interrupt */

#define HPC3_ERST_CLRIRQ 0x2	/* Clear channel interrupt */

#define HPC3_ERXRST_LBACK  0x4	/* Enable diagnostic loopback mode of Seeq8003 */

#define HPC3_ERST_LBACK  0x4	/* Enable diagnostic loopback mode of Seeq8003 */





	volatile u32 rx_dconfig;	/* DMA configuration register */

	volatile u32 dconfig;    /* DMA configuration register */

#define HPC3_ERXDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */

#define HPC3_EDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */

#define HPC3_ERXDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */

#define HPC3_EDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */

#define HPC3_ERXDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */

#define HPC3_EDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */

#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */

#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */

#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */

#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */

#define HPC3_ERXDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */

#define HPC3_EDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */

#define HPC3_ERXDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */

#define HPC3_EDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */

#define HPC3_ERXDCFG_PTO   0x30000 /* Programmed timeout value for above two */

#define HPC3_EDCFG_PTO   0x30000 /* Programmed timeout value for above two */





	volatile u32 rx_pconfig;	/* PIO configuration register */

	volatile u32 pconfig;   /* PIO configuration register */

#define HPC3_ERXPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */

#define HPC3_EPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */

#define HPC3_ERXPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */

#define HPC3_EPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */

#define HPC3_ERXPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */

#define HPC3_EPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */

#define HPC3_ERXPCFG_TST   0x1000 /* Diagnistic ram test feature bit */

#define HPC3_EPCFG_TST   0x1000 /* Diagnistic ram test feature bit */





	u32 _unused2[0x1000/4 - 8];	/* padding */

	u32 _unused2[0x1000/4 - 8];	/* padding */