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Commit 2ed8c243 authored by Jayadev K's avatar Jayadev K
Browse files

ARM: dts: qcom: Add device tree support for hsi2s driver 



Adding device nodes for hsi2s interfaces in the sa6155 adp air
device tree.

Change-Id: If739bb32048fb5c208ffca5be2d380a134894fbf
Signed-off-by: default avatarJayadev K <jayak@codeaurora.org>
parent a6835f15

arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -42,6 +42,53 @@ 
			status = "disabled";

		};

	};



	hsi2s: qcom,hsi2s {

		compatible = "qcom,hsi2s";

		number-of-interfaces = <2>;

		reg = <0x1B40000 0x28000>;

		reg-names = "lpa_if";

		interrupts = <GIC_SPI 267 0>;

		clocks = <&clock_gcc GCC_SDR_CORE_CLK>,

			 <&clock_gcc GCC_SDR_WR0_MEM_CLK>,

			 <&clock_gcc GCC_SDR_WR1_MEM_CLK>,

			 <&clock_gcc GCC_SDR_WR2_MEM_CLK>,

			 <&clock_gcc GCC_SDR_CSR_HCLK>;

		clock-names = "core_clk", "wr0_mem_clk",

			      "wr1_mem_clk", "wr2_mem_clk",

			      "csr_hclk";



		sdr0: qcom,hs0_i2s {

			compatible = "qcom,hsi2s-interface";

			minor-number = <0>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_data0_active

				     &hs0_i2s_data1_active>;

			pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_data0_sleep

				     &hs0_i2s_data1_sleep>;

			clocks = <&clock_gcc GCC_SDR_PRI_MI2S_CLK>;

			clock-names = "pri_mi2s_clk";

			iommus = <&apps_smmu 0x035C 0x0>;

			qcom,smmu-s1-bypass;

			qcom,iova-mapping = <0x0 0xFFFFFFFF>;

		};



		sdr1: qcom,hs1_i2s {

			compatible = "qcom,hsi2s-interface";

			minor-number = <1>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_data0_active

				     &hs1_i2s_data1_active>;

			pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_data0_sleep

				     &hs1_i2s_data1_sleep>;

			clocks = <&clock_gcc GCC_SDR_SEC_MI2S_CLK>;

			clock-names = "sec_mi2s_clk";

			iommus = <&apps_smmu 0x035D 0x0>;

			qcom,smmu-s1-bypass;

			qcom,iova-mapping = <0x0 0xFFFFFFFF>;

		};

	};



	emac_hw: qcom,emac@20000 {

		compatible = "qcom,emac-dwc-eqos";

		qcom,arm-smmu;