ARM: dts: msm: Fix clock entries for SDE on SDM855



This change fixes the clock rate and max rate entries for
SDE clocks so that core clock and vsync clk rates match
with the required rates.

Change-Id: Ie16f273d127b9667b4fb7afcb4a582d9c18eef44
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>

parent b2bdf7dc

arch/arm64/boot/dts/qcom/sdm855-sde.dtsi

+2 −2

Original line number	Diff line number	Diff line
		@@ -29,8 +29,8 @@
		<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
		clock-names = "gcc_iface", "gcc_bus",
		"iface_clk", "core_clk", "vsync_clk";
		clock-rate = <0 0 0 0 300000000 19200000 0>;
		clock-max-rate = <0 0 0 0 412500000 19200000 0>;
		clock-rate = <0 0 0 300000000 19200000>;
		clock-max-rate = <0 0 0 460000000 19200000>;

		sde-vdd-supply = <&mdss_core_gdsc>;