Merge changes Iee98837f,Ic9666576,I05b25314,I7bcf4347 into msm-next (2e1cfbd5) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt

+47 −8

Original line number	Diff line number	Diff line
		@@ -43,6 +43,17 @@ PMIC's from Qualcomm.
		the first cell will be used to define gpio number and the
		second denotes the flags for this gpio

		- qcom,gpios-disallowed:
		Usage: optional
		Value type: <prop-encoded-array>
		Definition: Array of the GPIO hardware numbers corresponding to GPIOs
		which the APSS processor is not allowed to configure.
		The hardware numbers are indexed from 1.
		The interrupt resources for these GPIOs must not be defined
		in "interrupts" and "interrupt-names" properties.
		GPIOs defined in this array won't be registered as pins
		in the pinctrl device or gpios in the gpio chip.

		Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
		a general description of GPIO and interrupt bindings.

		@@ -98,7 +109,11 @@ to specify in a pin configuration subnode:
		"dtest1",
		"dtest2",
		"dtest3",
		"dtest4"
		"dtest4",
		And following values are supported by LV/MV GPIO subtypes:
		"func3",
		"func4",
		"analog"

		- bias-disable:
		Usage: optional
		@@ -183,6 +198,29 @@ to specify in a pin configuration subnode:
		Value type: <none>
		Definition: The specified pins are configured in open-source mode.

		- qcom,atest:
		Usage: optional
		Value type: <u32>
		Definition: Selects ATEST rail to route to GPIO when it's configured
		in analog-pass-through mode by specifying "analog" function.
		Valid values are 0-3 corresponding to PMIC_GPIO_AOUT_ATESTx
		defined in <dt-bindings/pinctrl/qcom,pmic-gpio.h>.

		- qcom,dtest-buffer:
		Usage: optional
		Value type: <u32>
		Definition: Selects DTEST rail to route to GPIO when it's configured
		as a digital input.
		For LV/MV GPIO subtypes, the valid values are 0-3
		corresponding to PMIC_GPIO_DIN_DTESTx defined in
		<dt-bindings/pinctrl/qcom,pmic-gpio.h>. Only one
		DTEST rail can be selected at a time.
		For 4CH/8CH GPIO subtypes, supported values are 1-15.
		4 DTEST rails are supported in total and more than 1 DTEST
		rail can be selected simultaneously. Each bit of the
		4 LSBs represent one DTEST rail, such as [3:0] = 0101
		means both DTEST1 and DTEST3 are selected.

		Example:

		pm8921_gpio: gpio@150 {
		@@ -206,6 +244,7 @@ Example:

		gpio-controller;
		#gpio-cells = <2>;
		qcom,gpios-disallowed = <1 20>;

		pm8921_gpio_keys: gpio-keys {
		volume-keys {

drivers/pinctrl/qcom/pinctrl-spmi-gpio.c

+446 −74

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
		* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -40,6 +40,8 @@
		#define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
		#define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
		#define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
		#define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
		#define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11

		#define PMIC_MPP_REG_RT_STS 0x10
		#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
		@@ -48,8 +50,11 @@
		#define PMIC_GPIO_REG_MODE_CTL 0x40
		#define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
		#define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
		#define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
		#define PMIC_GPIO_REG_DIG_IN_CTL 0x43
		#define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
		#define PMIC_GPIO_REG_EN_CTL 0x46
		#define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A

		/* PMIC_GPIO_REG_MODE_CTL */
		#define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
		@@ -58,6 +63,13 @@
		#define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
		#define PMIC_GPIO_REG_MODE_DIR_MASK 0x7

		#define PMIC_GPIO_MODE_DIGITAL_INPUT 0
		#define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
		#define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
		#define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3

		#define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3

		/* PMIC_GPIO_REG_DIG_VIN_CTL */
		#define PMIC_GPIO_REG_VIN_SHIFT 0
		#define PMIC_GPIO_REG_VIN_MASK 0x7
		@@ -69,6 +81,16 @@
		#define PMIC_GPIO_PULL_DOWN 4
		#define PMIC_GPIO_PULL_DISABLE 5

		/* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
		#define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
		#define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
		#define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF

		/* PMIC_GPIO_REG_DIG_IN_CTL */
		#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
		#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
		#define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf

		/* PMIC_GPIO_REG_DIG_OUT_CTL */
		#define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
		#define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
		@@ -88,41 +110,70 @@

		#define PMIC_GPIO_PHYSICAL_OFFSET 1

		/* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
		#define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3

		/* Qualcomm specific pin configurations */
		#define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
		#define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
		#define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
		#define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 4)

		/* The index of each function in pmic_gpio_functions[] array */
		enum pmic_gpio_func_index {
		PMIC_GPIO_FUNC_INDEX_NORMAL = 0x00,
		PMIC_GPIO_FUNC_INDEX_PAIRED = 0x01,
		PMIC_GPIO_FUNC_INDEX_FUNC1 = 0x02,
		PMIC_GPIO_FUNC_INDEX_FUNC2 = 0x03,
		PMIC_GPIO_FUNC_INDEX_FUNC3 = 0x04,
		PMIC_GPIO_FUNC_INDEX_FUNC4 = 0x05,
		PMIC_GPIO_FUNC_INDEX_DTEST1 = 0x06,
		PMIC_GPIO_FUNC_INDEX_DTEST2 = 0x07,
		PMIC_GPIO_FUNC_INDEX_DTEST3 = 0x08,
		PMIC_GPIO_FUNC_INDEX_DTEST4 = 0x09,
		PMIC_GPIO_FUNC_INDEX_ANALOG = 0x10,
		};

		/**
		* struct pmic_gpio_pad - keep current GPIO settings
		* @base: Address base in SPMI device.
		* @irq: IRQ number which this GPIO generate.
		* @gpio_idx: The index in GPIO's hardware number space (1-based)
		* @is_enabled: Set to false when GPIO should be put in high Z state.
		* @out_value: Cached pin output value
		* @have_buffer: Set to true if GPIO output could be configured in push-pull,
		* open-drain or open-source mode.
		* @output_enabled: Set to true if GPIO output logic is enabled.
		* @input_enabled: Set to true if GPIO input buffer logic is enabled.
		* @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
		* @num_sources: Number of power-sources supported by this GPIO.
		* @power_source: Current power-source used.
		* @buffer_type: Push-pull, open-drain or open-source.
		* @pullup: Constant current which flow trough GPIO output buffer.
		* @strength: No, Low, Medium, High
		* @function: See pmic_gpio_functions[]
		* @atest: the ATEST selection for GPIO analog-pass-through mode
		* @dtest_buffer: the DTEST buffer selection for digital input mode,
		* the default value is INT_MAX if not used.
		*/
		struct pmic_gpio_pad {
		u16 base;
		int irq;
		int gpio_idx;
		bool is_enabled;
		bool out_value;
		bool have_buffer;
		bool output_enabled;
		bool input_enabled;
		bool lv_mv_type;
		unsigned int num_sources;
		unsigned int power_source;
		unsigned int buffer_type;
		unsigned int pullup;
		unsigned int strength;
		unsigned int function;
		unsigned int atest;
		unsigned int dtest_buffer;
		};

		struct pmic_gpio_state {
		@@ -130,17 +181,21 @@ struct pmic_gpio_state {
		struct regmap *map;
		struct pinctrl_dev *ctrl;
		struct gpio_chip chip;
		const char **gpio_groups;
		};

		static const struct pinconf_generic_params pmic_gpio_bindings[] = {
		{"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
		{"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
		{"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
		{"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
		};

		#ifdef CONFIG_DEBUG_FS
		static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
		PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
		PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
		PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
		};
		#endif

		@@ -152,11 +207,25 @@ static const char *const pmic_gpio_groups[] = {
		"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
		};

		/*
		* Treat LV/MV GPIO analog-pass-through mode as a function, add it
		* to the end of the function list. Add placeholder for the reserved
		* functions defined in LV/MV OUTPUT_SOURCE_SEL register.
		*/
		static const char *const pmic_gpio_functions[] = {
		PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
		PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
		PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
		PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
		[PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
		[PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
		[PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
		[PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
		[PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
		[PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
		[PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
		[PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
		[PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
		[PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
		"reserved-a", "reserved-b", "reserved-c",
		"reserved-d", "reserved-e", "reserved-f",
		[PMIC_GPIO_FUNC_INDEX_ANALOG] = PMIC_GPIO_FUNC_ANALOG,
		};

		static int pmic_gpio_read(struct pmic_gpio_state *state,
		@@ -231,7 +300,9 @@ static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
		const char const *groups,
		unsigned *const num_qgroups)
		{
		*groups = pmic_gpio_groups;
		struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);

		*groups = state->gpio_groups;
		*num_qgroups = pctldev->desc->npins;
		return 0;
		}
		@@ -248,12 +319,64 @@ static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,

		pad->function = function;

		val = 0;
		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
		if (pad->output_enabled) {
		if (pad->input_enabled)
		val = 2;
		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
		else
		val = 1;
		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
		}

		if (function > PMIC_GPIO_FUNC_INDEX_DTEST4 &&
		function < PMIC_GPIO_FUNC_INDEX_ANALOG) {
		pr_err("reserved function: %s hasn't been enabled\n",
		pmic_gpio_functions[function]);
		return -EINVAL;
		}

		if (pad->lv_mv_type) {
		if (pad->function == PMIC_GPIO_FUNC_INDEX_ANALOG) {
		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
		ret = pmic_gpio_write(state, pad,
		PMIC_GPIO_REG_MODE_CTL, val);
		if (ret < 0)
		return ret;

		ret = pmic_gpio_write(state, pad,
		PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL,
		pad->atest);
		if (ret < 0)
		return ret;
		} else {
		ret = pmic_gpio_write(state, pad,
		PMIC_GPIO_REG_MODE_CTL, val);
		if (ret < 0)
		return ret;

		val = pad->out_value
		<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
		val \|= pad->function
		& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
		ret = pmic_gpio_write(state, pad,
		PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
		if (ret < 0)
		return ret;
		}
		} else {
		/*
		* GPIO not of LV/MV subtype doesn't have "func3", "func4"
		* "analog" functions, and "dtest1" to "dtest4" functions
		* have register value 2 bits lower than the function index
		* in pmic_gpio_functions[].
		*/
		if (function == PMIC_GPIO_FUNC_INDEX_FUNC3
		\|\| function == PMIC_GPIO_FUNC_INDEX_FUNC4
		\|\| function == PMIC_GPIO_FUNC_INDEX_ANALOG) {
		return -EINVAL;
		} else if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1 &&
		function <= PMIC_GPIO_FUNC_INDEX_DTEST4) {
		pad->function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
		PMIC_GPIO_FUNC_INDEX_FUNC3);
		}

		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
		@@ -263,6 +386,7 @@ static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
		if (ret < 0)
		return ret;
		}

		val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;

		@@ -322,6 +446,12 @@ static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
		case PMIC_GPIO_CONF_STRENGTH:
		arg = pad->strength;
		break;
		case PMIC_GPIO_CONF_ATEST:
		arg = pad->atest;
		break;
		case PMIC_GPIO_CONF_DTEST_BUFFER:
		arg = pad->dtest_buffer;
		break;
		default:
		return -EINVAL;
		}
		@@ -375,7 +505,7 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
		pad->is_enabled = false;
		break;
		case PIN_CONFIG_POWER_SOURCE:
		if (arg > pad->num_sources)
		if (arg >= pad->num_sources)
		return -EINVAL;
		pad->power_source = arg;
		break;
		@@ -396,6 +526,18 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
		return -EINVAL;
		pad->strength = arg;
		break;
		case PMIC_GPIO_CONF_ATEST:
		if (arg > PMIC_GPIO_AOUT_ATEST4)
		return -EINVAL;
		pad->atest = arg;
		break;
		case PMIC_GPIO_CONF_DTEST_BUFFER:
		if ((pad->lv_mv_type && arg > PMIC_GPIO_DIN_DTEST4)
		\|\| (!pad->lv_mv_type && arg >
		PMIC_GPIO_DIG_IN_DTEST_SEL_MASK))
		return -EINVAL;
		pad->dtest_buffer = arg;
		break;
		default:
		return -EINVAL;
		}
		@@ -420,19 +562,64 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
		if (ret < 0)
		return ret;

		val = 0;
		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
		if (pad->output_enabled) {
		if (pad->input_enabled)
		val = 2;
		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
		else
		val = 1;
		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
		}

		if (pad->dtest_buffer != INT_MAX) {
		val = pad->dtest_buffer;
		if (pad->lv_mv_type)
		val \|= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;

		ret = pmic_gpio_write(state, pad,
		PMIC_GPIO_REG_DIG_IN_CTL, val);
		if (ret < 0)
		return ret;
		}

		if (pad->lv_mv_type) {
		if (pad->function == PMIC_GPIO_FUNC_INDEX_ANALOG) {
		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
		ret = pmic_gpio_write(state, pad,
		PMIC_GPIO_REG_MODE_CTL, val);
		if (ret < 0)
		return ret;

		ret = pmic_gpio_write(state, pad,
		PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL,
		pad->atest);
		if (ret < 0)
		return ret;
		} else {
		ret = pmic_gpio_write(state, pad,
		PMIC_GPIO_REG_MODE_CTL, val);
		if (ret < 0)
		return ret;

		val = pad->out_value
		<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
		val \|= pad->function
		& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
		ret = pmic_gpio_write(state, pad,
		PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
		if (ret < 0)
		return ret;
		}
		} else {
		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
		val \|= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
		val \|= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;

		return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
		if (ret < 0)
		return ret;
		}

		return ret;
		}

		static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
		@@ -440,7 +627,7 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
		{
		struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
		struct pmic_gpio_pad *pad;
		int ret, val;
		int ret, val, function;

		static const char *const biases[] = {
		"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
		@@ -455,7 +642,7 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,

		pad = pctldev->desc->pins[pin].drv_data;

		seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
		seq_printf(s, " gpio%-2d:", pad->gpio_idx);

		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);

		@@ -471,14 +658,28 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
		ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
		pad->out_value = ret;
		}
		/*
		* For GPIO not of LV/MV subtypes, the register value of
		* the function mapping from "dtest1" to "dtest4" is 2 bits
		* lower than the function index in pmic_gpio_functions[].
		*/
		if (!pad->lv_mv_type &&
		pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3) {
		function = pad->function + (PMIC_GPIO_FUNC_INDEX_DTEST1
		- PMIC_GPIO_FUNC_INDEX_FUNC3);
		} else {
		function = pad->function;
		}

		seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
		seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]);
		seq_printf(s, " %-7s", pmic_gpio_functions[function]);
		seq_printf(s, " vin-%d", pad->power_source);
		seq_printf(s, " %-27s", biases[pad->pullup]);
		seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
		seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
		seq_printf(s, " %-7s", strengths[pad->strength]);
		if (pad->dtest_buffer != INT_MAX)
		seq_printf(s, " dtest buffer %d", pad->dtest_buffer);
		}
		}

		@@ -546,13 +747,29 @@ static int pmic_gpio_of_xlate(struct gpio_chip *chip,
		const struct of_phandle_args *gpio_desc,
		u32 *flags)
		{
		int i;
		struct pmic_gpio_state *state = gpiochip_get_data(chip);
		struct pinctrl_desc *desc = state->ctrl->desc;
		struct pmic_gpio_pad *pad;

		if (chip->of_gpio_n_cells < 2)
		return -EINVAL;

		if (flags)
		*flags = gpio_desc->args[1];

		return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
		for (i = 0; i < chip->ngpio; i++) {
		pad = desc->pins[i].drv_data;
		if (pad->gpio_idx == gpio_desc->args[0]) {
		dev_dbg(state->dev, "gpio%-2d xlate to pin%-2d\n",
		gpio_desc->args[0], i);
		return i;
		}
		}

		dev_err(state->dev, "Couldn't find pin for gpio %d\n",
		gpio_desc->args[0]);
		return -ENODEV;
		}

		static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
		@@ -618,11 +835,36 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
		case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
		pad->num_sources = 8;
		break;
		case PMIC_GPIO_SUBTYPE_GPIO_LV:
		pad->num_sources = 1;
		pad->have_buffer = true;
		pad->lv_mv_type = true;
		break;
		case PMIC_GPIO_SUBTYPE_GPIO_MV:
		pad->num_sources = 2;
		pad->have_buffer = true;
		pad->lv_mv_type = true;
		break;
		default:
		dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
		return -ENODEV;
		}

		if (pad->lv_mv_type) {
		val = pmic_gpio_read(state, pad,
		PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
		if (val < 0)
		return val;

		pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
		pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;

		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
		if (val < 0)
		return val;

		dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
		} else {
		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
		if (val < 0)
		return val;
		@@ -631,27 +873,34 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,

		dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
		dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
		pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
		pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
		}

		switch (dir) {
		case 0:
		case PMIC_GPIO_MODE_DIGITAL_INPUT:
		pad->input_enabled = true;
		pad->output_enabled = false;
		break;
		case 1:
		case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
		pad->input_enabled = false;
		pad->output_enabled = true;
		break;
		case 2:
		case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
		pad->input_enabled = true;
		pad->output_enabled = true;
		break;
		case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
		if (pad->lv_mv_type)
		pad->function = PMIC_GPIO_FUNC_INDEX_ANALOG;
		else
		return -ENODEV;
		break;
		default:
		dev_err(state->dev, "unknown GPIO direction\n");
		return -ENODEV;
		}

		pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
		pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;

		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
		if (val < 0)
		return val;
		@@ -666,6 +915,17 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
		pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
		pad->pullup &= PMIC_GPIO_REG_PULL_MASK;

		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
		if (val < 0)
		return val;

		if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
		pad->dtest_buffer = val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK;
		else if (!pad->lv_mv_type)
		pad->dtest_buffer = val & PMIC_GPIO_DIG_IN_DTEST_SEL_MASK;
		else
		pad->dtest_buffer = INT_MAX;

		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
		if (val < 0)
		return val;
		@@ -676,6 +936,13 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
		pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
		pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;

		if (pad->function == PMIC_GPIO_FUNC_INDEX_ANALOG) {
		val = pmic_gpio_read(state, pad,
		PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
		if (val < 0)
		return val;
		pad->atest = val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK;
		}
		/* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
		pad->is_enabled = true;
		return 0;
		@@ -688,43 +955,124 @@ static int pmic_gpio_probe(struct platform_device *pdev)
		struct pinctrl_desc *pctrldesc;
		struct pmic_gpio_pad pad, pads;
		struct pmic_gpio_state *state;
		int ret, npins, i;
		u32 reg;
		int ret, npins, ngpios, i, j, pin_idx;
		int disallowed_count = 0;
		u32 reg[2], start, size;
		u32 *disallowed = NULL;

		ret = of_property_read_u32(dev->of_node, "reg", &reg);
		ret = of_property_read_u32_array(dev->of_node, "reg", reg, 2);
		if (ret < 0) {
		dev_err(dev, "missing base address");
		dev_err(dev, "reg property reading failed\n");
		return ret;
		}
		start = reg[0];
		size = reg[1];

		ngpios = size / PMIC_GPIO_ADDRESS_RANGE;
		if (ngpios == 0) {
		dev_err(dev, "no gpios assigned\n");
		return -ENODEV;
		}

		npins = platform_irq_count(pdev);
		if (!npins)
		if (ngpios > ARRAY_SIZE(pmic_gpio_groups)) {
		dev_err(dev, "reg property defines %d gpios, but only %d are allowed\n",
		ngpios, (int)ARRAY_SIZE(pmic_gpio_groups));
		return -EINVAL;
		if (npins < 0)
		return npins;
		}

		BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
		if (of_find_property(dev->of_node, "qcom,gpios-disallowed",
		&disallowed_count)) {
		disallowed_count /= sizeof(u32);
		if (disallowed_count == 0) {
		dev_err(dev, "No data in gpios-disallowed\n");
		return -EINVAL;
		}

		state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
		if (!state)
		disallowed = kcalloc(disallowed_count, sizeof(u32), GFP_KERNEL);
		if (disallowed == NULL)
		return -ENOMEM;

		ret = of_property_read_u32_array(dev->of_node,
		"qcom,gpios-disallowed",
		disallowed, disallowed_count);
		if (ret < 0) {
		dev_err(dev, "qcom,gpios-disallowed property reading failed, ret=%d\n",
		ret);
		goto err_free;
		}

		for (i = 0; i < disallowed_count; i++) {
		if (disallowed[i] >= ngpios + PMIC_GPIO_PHYSICAL_OFFSET
		\|\| disallowed[i] < PMIC_GPIO_PHYSICAL_OFFSET) {
		dev_err(dev, "invalid gpio = %d specified in qcom,gpios-disallowed, supported values: %d to %d\n",
		disallowed[i],
		PMIC_GPIO_PHYSICAL_OFFSET,
		ngpios - 1 + PMIC_GPIO_PHYSICAL_OFFSET);
		ret = -EINVAL;
		goto err_free;
		}
		for (j = 0; j < i; j++) {
		if (disallowed[i] == disallowed[j]) {
		dev_err(dev, "duplicate gpio = %d listed in qcom,gpios-disallowed\n",
		disallowed[i]);
		ret = -EINVAL;
		goto err_free;
		}
		}
		dev_dbg(dev, "gpio %d NOT supported\n", disallowed[i]);
		}
		} else {
		disallowed_count = 0;
		}

		npins = ngpios - disallowed_count;
		if (npins <= 0) {
		dev_err(dev, "No pins assigned\n");
		ret = -ENODEV;
		goto err_free;
		}
		if (platform_irq_count(pdev) != npins) {
		dev_err(dev, "%d IRQs defined but %d expected\n",
		platform_irq_count(pdev), npins);
		ret = -EINVAL;
		goto err_free;
		}

		state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
		if (!state) {
		ret = -ENOMEM;
		goto err_free;
		}

		platform_set_drvdata(pdev, state);

		state->dev = &pdev->dev;
		state->map = dev_get_regmap(dev->parent, NULL);

		state->gpio_groups = devm_kcalloc(dev, sizeof(*state->gpio_groups),
		npins, GFP_KERNEL);
		if (!state->gpio_groups) {
		ret = -ENOMEM;
		goto err_free;
		}

		pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
		if (!pindesc)
		return -ENOMEM;
		if (!pindesc) {
		ret = -ENOMEM;
		goto err_free;
		}

		pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
		if (!pads)
		return -ENOMEM;
		if (!pads) {
		ret = -ENOMEM;
		goto err_free;
		}

		pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
		if (!pctrldesc)
		return -ENOMEM;
		if (!pctrldesc) {
		ret = -ENOMEM;
		goto err_free;
		}

		pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
		pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
		@@ -738,22 +1086,42 @@ static int pmic_gpio_probe(struct platform_device *pdev)
		#ifdef CONFIG_DEBUG_FS
		pctrldesc->custom_conf_items = pmic_conf_items;
		#endif
		for (pin_idx = 0, i = 0; i < ngpios; i++) {
		for (j = 0; j < disallowed_count; j++) {
		if (i + PMIC_GPIO_PHYSICAL_OFFSET == disallowed[j])
		break;
		}
		if (j != disallowed_count)
		continue;

		for (i = 0; i < npins; i++, pindesc++) {
		pad = &pads[i];
		pad = &pads[pin_idx];
		pindesc->drv_data = pad;
		pindesc->number = i;
		pindesc->number = pin_idx;
		pindesc->name = pmic_gpio_groups[i];

		pad->irq = platform_get_irq(pdev, i);
		if (pad->irq < 0)
		return pad->irq;
		pad->gpio_idx = i + PMIC_GPIO_PHYSICAL_OFFSET;
		pad->irq = platform_get_irq(pdev, pin_idx);
		if (pad->irq < 0) {
		dev_err(state->dev,
		"failed to get irq for gpio %d (pin %d), ret=%d\n",
		pad->gpio_idx, pin_idx, pad->irq);
		ret = pad->irq;
		goto err_free;
		}
		/* Every pin is a group */
		state->gpio_groups[pin_idx] = pmic_gpio_groups[i];

		pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
		pad->base = start + i * PMIC_GPIO_ADDRESS_RANGE;

		ret = pmic_gpio_populate(state, pad);
		if (ret < 0)
		return ret;
		if (ret < 0) {
		dev_err(state->dev,
		"failed to populate gpio %d, ret=%d\n",
		i, ret);
		goto err_free;
		}
		pindesc++;
		pin_idx++;
		}

		state->chip = pmic_gpio_gpio_template;
		@@ -765,25 +1133,29 @@ static int pmic_gpio_probe(struct platform_device *pdev)
		state->chip.can_sleep = false;

		state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
		if (IS_ERR(state->ctrl))
		return PTR_ERR(state->ctrl);
		if (IS_ERR(state->ctrl)) {
		ret = PTR_ERR(state->ctrl);
		dev_err(state->dev, "failed to register pinctrl device, ret=%d\n",
		ret);
		goto err_free;
		}

		ret = gpiochip_add_data(&state->chip, state);
		if (ret) {
		dev_err(state->dev, "can't add gpio chip\n");
		return ret;
		dev_err(state->dev, "can't add gpio chip, ret=%d\n", ret);
		goto err_free;
		}

		ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
		if (ret) {
		dev_err(dev, "failed to add pin range\n");
		goto err_range;
		dev_err(dev, "failed to add pin range\n, ret=%d\n", ret);
		gpiochip_remove(&state->chip);
		goto err_free;
		}

		return 0;
		err_free:
		kfree(disallowed);

		err_range:
		gpiochip_remove(&state->chip);
		return ret;
		}