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Commit 2db5a3d9 authored by Farrukh Qurashi's avatar Farrukh Qurashi
Browse files

ARM: dts: msm: Add NPU device configuration on SM8150 



Add interrupt, MMU, system cache, clocks and power level device node
configurations required by latest NPU driver. The NPU driver uses
these nodes for integrating with other various subsystems.

Change-Id: If05b547b26ebbe1efe9d0d259f7750a520f7349e
Signed-off-by: default avatarFarrukh Qurashi <fqurashi@codeaurora.org>
parent f6a8cd99

arch/arm64/boot/dts/qcom/sm8150-npu.dtsi

+186 −11
Original line number Diff line number Diff line
@@ -11,23 +11,198 @@ 
 */



&soc {

	msm_npu: qcom,msm_npu {

	msm_npu: qcom,msm_npu@9800000 {

		compatible = "qcom,msm-npu";

		status = "ok";

		reg = <0x9800000 0x800000>;

		reg-names = "npu_base";

		interrupts = <0 346 0>;

		clocks = <&clock_npucc NPU_CC_XO_CLK>,

					<&clock_npucc NPU_CC_NPU_CORE_CLK>,

					<&clock_npucc NPU_CC_CAL_DP_CLK>,

		interrupts = <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>;

		iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>;

		cache-slice-names = "npu";

		cache-slices = <&llcc 23>;

		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,

				<&clock_npucc NPU_CC_CAL_DP_CLK_SRC>,

				<&clock_npucc NPU_CC_XO_CLK>,

				<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,

				<&clock_npucc NPU_CC_BTO_CORE_CLK>,

				<&clock_npucc NPU_CC_BWMON_CLK>,

				<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,

				<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

					<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>;

		clock-names = "xo", "core", "cal_dp", "armwic",

						"axi", "ahb";

				<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>,

				<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,

				<&clock_npucc NPU_CC_NPU_CPC_CLK>,

				<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,

				<&clock_npucc NPU_CC_PERF_CNT_CLK>,

				<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,

				<&clock_npucc NPU_CC_SLEEP_CLK>;

		clock-names = "cal_dp_clk",

				"cal_dp_clk_src",

				"xo_clk",

				"armwic_core_clk",

				"bto_core_clk",

				"bwmon_clk",

				"cal_dp_cdc_clk",

				"comp_noc_axi_clk",

				"conf_noc_ahb_clk",

				"npu_core_apb_clk",

				"npu_core_atb_clk",

				"npu_core_clk",

				"npu_core_clk_src",

				"npu_core_cti_clk",

				"npu_cpc_clk",

				"npu_cpc_timer_clk",

				"perf_cnt_clk",

				"qtimer_core_clk",

				"sleep_clk";

		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names ="vdd", "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>;

		mbox-names = "npu_low", "npu_high";

		#cooling-cells = <2>;

		qcom,npubw-dev = <&npu_npu_ddr_bw>;

		qcom,npu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,npu-pwrlevels";

			initial-pwrlevel = <4>;

			qcom,npu-pwrlevel@0 {

				reg = <0>;

				clk-freq = <9600000

						9600000

						19200000

						19200000

						19200000

						19200000

						9600000

						60000000

						19200000

						19200000

						30000000

						19200000

						19200000

						19200000

						19200000

						19200000

						9600000

						19200000

						0>;

			};

			qcom,npu-pwrlevel@1 {

				reg = <1>;

				clk-freq = <300000000

						300000000

						19200000

						100000000

						19200000

						19200000

						300000000

						150000000

						19200000

						19200000

						60000000

						100000000

						100000000

						37500000

						100000000

						19200000

						300000000

						19200000

						0>;

			};

			qcom,npu-pwrlevel@2 {

				reg = <2>;

				clk-freq = <350000000

						350000000

						19200000

						150000000

						19200000

						19200000

						350000000

						200000000

						37500000

						19200000

						120000000

						150000000

						150000000

						75000000

						150000000

						19200000

						350000000

						19200000

						0>;

			};

			qcom,npu-pwrlevel@3 {

				reg = <3>;

				clk-freq = <400000000

						400000000

						19200000

						200000000

						19200000

						19200000

						400000000

						300000000

						37500000

						19200000

						120000000

						200000000

						200000000

						75000000

						200000000

						19200000

						400000000

						19200000

						0>;

			};

			qcom,npu-pwrlevel@4 {

				reg = <4>;

				clk-freq = <600000000

						600000000

						19200000

						300000000

						19200000

						19200000

						600000000

						403000000

						75000000

						19200000

						240000000

						300000000

						300000000

						150000000

						300000000

						19200000

						600000000

						19200000

						0>;

			};

			qcom,npu-pwrlevel@5 {

				reg = <5>;

				clk-freq = <715000000

						715000000

						19200000

						350000000

						19200000

						19200000

						715000000

						533000000

						75000000

						19200000

						240000000

						350000000

						350000000

						150000000

						350000000

						19200000

						715000000

						19200000

						0>;

			};

		};

	};

};