Loading drivers/gpu/msm/adreno_a6xx_gmu.c +14 −2 Original line number Diff line number Diff line Loading @@ -139,8 +139,14 @@ static void _load_gmu_rpmh_ucode(struct kgsl_device *device) PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET, 0x0); _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108); if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30090); else _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30080); _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0); _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); Loading @@ -157,8 +163,14 @@ static void _load_gmu_rpmh_ucode(struct kgsl_device *device) PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET, 0x3); _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108); if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30090); else _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30080); _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x3); Loading Loading
drivers/gpu/msm/adreno_a6xx_gmu.c +14 −2 Original line number Diff line number Diff line Loading @@ -139,8 +139,14 @@ static void _load_gmu_rpmh_ucode(struct kgsl_device *device) PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET, 0x0); _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108); if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30090); else _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30080); _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0); _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); Loading @@ -157,8 +163,14 @@ static void _load_gmu_rpmh_ucode(struct kgsl_device *device) PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET, 0x3); _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108); if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30090); else _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30080); _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x3); Loading