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Commit 2d66eab1 authored by Varadarajan Narayanan's avatar Varadarajan Narayanan Committed by Kishon Vijay Abraham I
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dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074 



IPQ8074 uses QMP PHY controller that provides support to PCIe and
USB. Adding DT binding information for the same.

Reviewed-by: default avatarVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: default avatarVaradarajan Narayanan <varada@codeaurora.org>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent e88432e7

Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt

+8 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 


Required properties:

 - compatible: compatible list, contains:

	       "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074

	       "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,

	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
@@ -38,6 +39,8 @@ Required properties: 
		 "phy", "common", "cfg".

		For "qcom,msm8996-qmp-usb3-phy" must contain

		 "phy", "common".

		For "qcom,ipq8074-qmp-pcie-phy" must contain:

		 "phy", "common".



 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.

 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -63,6 +66,11 @@ Required properties for child node: 
 - clock-output-names: Name of the PHY clock that will be the parent for

		       the above pipe clock.



	For "qcom,ipq8074-qmp-pcie-phy":

		- "pcie20_phy0_pipe_clk"	Pipe Clock parent

			(or)

		  "pcie20_phy1_pipe_clk"



 - resets: a list of phandles and reset controller specifier pairs,

	   one for each entry in reset-names.

 - reset-names: Must contain following for pcie qmp phys: