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Commit 2d3584eb authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: update generated headers 



Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 657c63f0

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+9 −9
Original line number Diff line number Diff line
@@ -8,15 +8,15 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  60633 bytes, from 2015-05-20 14:48:19)



Copyright (C) 2013-2014 by the following authors:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14968 bytes, from 2015-05-20 20:12:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  67120 bytes, from 2015-08-14 23:22:03)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  63785 bytes, from 2015-08-14 18:27:06)



Copyright (C) 2013-2015 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)



Permission is hereby granted, free of charge, to any person obtaining

drivers/gpu/drm/msm/adreno/a3xx.xml.h

+24 −9
Original line number Diff line number Diff line
@@ -8,13 +8,13 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  60633 bytes, from 2015-05-20 14:48:19)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14968 bytes, from 2015-05-20 20:12:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  67120 bytes, from 2015-08-14 23:22:03)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  63785 bytes, from 2015-08-14 18:27:06)



Copyright (C) 2013-2015 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)
@@ -326,6 +326,13 @@ enum a3xx_tex_type { 
	A3XX_TEX_3D = 3,

};



enum a3xx_tex_msaa {

	A3XX_TPL1_MSAA1X = 0,

	A3XX_TPL1_MSAA2X = 1,

	A3XX_TPL1_MSAA4X = 2,

	A3XX_TPL1_MSAA8X = 3,

};



#define A3XX_INT0_RBBM_GPU_IDLE					0x00000001

#define A3XX_INT0_RBBM_AHB_ERROR				0x00000002

#define A3XX_INT0_RBBM_REG_TIMEOUT				0x00000004
@@ -2652,6 +2659,7 @@ static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 
#define REG_A3XX_VGT_IMMED_DATA					0x000021fd



#define REG_A3XX_TEX_SAMP_0					0x00000000

#define A3XX_TEX_SAMP_0_CLAMPENABLE				0x00000001

#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR			0x00000002

#define A3XX_TEX_SAMP_0_XY_MAG__MASK				0x0000000c

#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT				2
@@ -2695,6 +2703,7 @@ static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val 
{

	return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;

}

#define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF			0x01000000

#define A3XX_TEX_SAMP_0_UNNORM_COORDS				0x80000000



#define REG_A3XX_TEX_SAMP_1					0x00000001
@@ -2750,6 +2759,12 @@ static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) 
{

	return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;

}

#define A3XX_TEX_CONST_0_MSAATEX__MASK				0x00300000

#define A3XX_TEX_CONST_0_MSAATEX__SHIFT				20

static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val)

{

	return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK;

}

#define A3XX_TEX_CONST_0_FMT__MASK				0x1fc00000

#define A3XX_TEX_CONST_0_FMT__SHIFT				22

static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
@@ -2785,7 +2800,7 @@ static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) 
}



#define REG_A3XX_TEX_CONST_2					0x00000002

#define A3XX_TEX_CONST_2_INDX__MASK				0x000000ff

#define A3XX_TEX_CONST_2_INDX__MASK				0x000001ff

#define A3XX_TEX_CONST_2_INDX__SHIFT				0

static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)

{
@@ -2805,7 +2820,7 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 
}



#define REG_A3XX_TEX_CONST_3					0x00000003

#define A3XX_TEX_CONST_3_LAYERSZ1__MASK				0x00007fff

#define A3XX_TEX_CONST_3_LAYERSZ1__MASK				0x0001ffff

#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT			0

static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)

{

drivers/gpu/drm/msm/adreno/a4xx.xml.h

+197 −9
Original line number Diff line number Diff line
@@ -8,13 +8,13 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  60633 bytes, from 2015-05-20 14:48:19)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14968 bytes, from 2015-05-20 20:12:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  67120 bytes, from 2015-08-14 23:22:03)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  63785 bytes, from 2015-08-14 18:27:06)



Copyright (C) 2013-2015 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)
@@ -227,6 +227,7 @@ enum a4xx_depth_format { 
	DEPTH4_NONE = 0,

	DEPTH4_16 = 1,

	DEPTH4_24_8 = 2,

	DEPTH4_32 = 3,

};



enum a4xx_tess_spacing {
@@ -429,7 +430,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 
	return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;

}

#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB				0x00002000

#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK		0x007fc000

#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK		0xffffc000

#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT		14

static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)

{
@@ -439,7 +440,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 
static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }



static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }

#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK			0x0001fff8

#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK			0x03fffff8

#define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT			3

static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)

{
@@ -570,6 +571,15 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 
	return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;

}



#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL			0x000020fa

#define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002

#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK			0xfffffffc

#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT		2

static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)

{

	return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;

}



#define REG_A4XX_RB_RENDER_COMPONENTS				0x000020fb

#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK			0x0000000f

#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT			0
@@ -811,6 +821,23 @@ static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v 
#define REG_A4XX_RB_STENCIL_CONTROL2				0x00002107

#define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER			0x00000001



#define REG_A4XX_RB_STENCIL_INFO				0x00002108

#define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL			0x00000001

#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK			0xfffff000

#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT		12

static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)

{

	return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;

}



#define REG_A4XX_RB_STENCIL_PITCH				0x00002109

#define A4XX_RB_STENCIL_PITCH__MASK				0xffffffff

#define A4XX_RB_STENCIL_PITCH__SHIFT				0

static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)

{

	return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;

}



#define REG_A4XX_RB_STENCILREFMASK				0x0000210b

#define A4XX_RB_STENCILREFMASK_STENCILREF__MASK			0x000000ff

#define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT		0
@@ -1433,6 +1460,7 @@ static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 
{

	return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;

}

#define A4XX_SP_FS_MRT_REG_COLOR_SRGB				0x00040000



#define REG_A4XX_SP_CS_CTRL_REG0				0x00002300
@@ -1470,6 +1498,76 @@ static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 


#define REG_A4XX_SP_HS_LENGTH_REG				0x00002312



#define REG_A4XX_SP_DS_PARAM_REG				0x0000231a

#define A4XX_SP_DS_PARAM_REG_POSREGID__MASK			0x000000ff

#define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT			0

static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)

{

	return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;

}

#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK		0xfff00000

#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT		20

static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)

{

	return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;

}



static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }



static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }

#define A4XX_SP_DS_OUT_REG_A_REGID__MASK			0x000001ff

#define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT			0

static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)

{

	return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;

}

#define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK			0x00001e00

#define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT			9

static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)

{

	return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;

}

#define A4XX_SP_DS_OUT_REG_B_REGID__MASK			0x01ff0000

#define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT			16

static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)

{

	return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;

}

#define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK			0x1e000000

#define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT			25

static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)

{

	return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;

}



static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }



static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }

#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff

#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT			0

static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)

{

	return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;

}

#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00

#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT			8

static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)

{

	return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;

}

#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000

#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT			16

static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)

{

	return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;

}

#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK			0xff000000

#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT			24

static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)

{

	return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;

}



#define REG_A4XX_SP_DS_OBJ_OFFSET_REG				0x00002334

#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000

#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
@@ -1492,6 +1590,82 @@ static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 


#define REG_A4XX_SP_DS_LENGTH_REG				0x00002339



#define REG_A4XX_SP_GS_PARAM_REG				0x00002341

#define A4XX_SP_GS_PARAM_REG_POSREGID__MASK			0x000000ff

#define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT			0

static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)

{

	return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;

}

#define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK			0x0000ff00

#define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT			8

static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)

{

	return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;

}

#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK		0xfff00000

#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT		20

static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)

{

	return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;

}



static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }



static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }

#define A4XX_SP_GS_OUT_REG_A_REGID__MASK			0x000001ff

#define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT			0

static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)

{

	return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;

}

#define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK			0x00001e00

#define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT			9

static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)

{

	return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;

}

#define A4XX_SP_GS_OUT_REG_B_REGID__MASK			0x01ff0000

#define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT			16

static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)

{

	return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;

}

#define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK			0x1e000000

#define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT			25

static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)

{

	return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;

}



static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }



static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }

#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff

#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT			0

static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)

{

	return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;

}

#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00

#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT			8

static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)

{

	return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;

}

#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000

#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT			16

static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)

{

	return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;

}

#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK			0xff000000

#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT			24

static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)

{

	return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;

}



#define REG_A4XX_SP_GS_OBJ_OFFSET_REG				0x0000235b

#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000

#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
@@ -1693,6 +1867,18 @@ static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) 
{

	return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;

}

#define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK			0x00ff0000

#define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT			16

static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)

{

	return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;

}

#define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK			0xff000000

#define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT			24

static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)

{

	return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;

}



#define REG_A4XX_VFD_CONTROL_4					0x00002204
@@ -2489,6 +2675,8 @@ static inline uint32_t A4XX_UNKNOWN_20F7(float val) 


#define REG_A4XX_UNKNOWN_22D7					0x000022d7



#define REG_A4XX_UNKNOWN_2352					0x00002352



#define REG_A4XX_TEX_SAMP_0					0x00000000

#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR			0x00000001

#define A4XX_TEX_SAMP_0_XY_MAG__MASK				0x00000006

drivers/gpu/drm/msm/adreno/adreno_common.xml.h

+9 −9
Original line number Diff line number Diff line
@@ -8,15 +8,15 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  60633 bytes, from 2015-05-20 14:48:19)



Copyright (C) 2013-2014 by the following authors:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14968 bytes, from 2015-05-20 20:12:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  67120 bytes, from 2015-08-14 23:22:03)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  63785 bytes, from 2015-08-14 18:27:06)



Copyright (C) 2013-2015 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)



Permission is hereby granted, free of charge, to any person obtaining

drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h

+9 −9
Original line number Diff line number Diff line
@@ -8,13 +8,13 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  60633 bytes, from 2015-05-20 14:48:19)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14968 bytes, from 2015-05-20 20:12:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  67120 bytes, from 2015-08-14 23:22:03)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  63785 bytes, from 2015-08-14 18:27:06)



Copyright (C) 2013-2015 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)
@@ -67,7 +67,7 @@ enum vgt_event_type { 


enum pc_di_primtype {

	DI_PT_NONE = 0,

	DI_PT_POINTLIST_A2XX = 1,

	DI_PT_POINTLIST_PSIZE = 1,

	DI_PT_LINELIST = 2,

	DI_PT_LINESTRIP = 3,

	DI_PT_TRILIST = 4,
@@ -75,7 +75,7 @@ enum pc_di_primtype { 
	DI_PT_TRISTRIP = 6,

	DI_PT_LINELOOP = 7,

	DI_PT_RECTLIST = 8,

	DI_PT_POINTLIST_A3XX = 9,

	DI_PT_POINTLIST = 9,

	DI_PT_LINE_ADJ = 10,

	DI_PT_LINESTRIP_ADJ = 11,

	DI_PT_TRI_ADJ = 12,