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Commit 2cb8cb14 authored by Vivien Didelot's avatar Vivien Didelot Committed by David S. Miller
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net: dsa: mv88e6xxx: prefix Port Egress Rate Control macros 



For implicit namespacing and clarity, prefix the common Port Egress Rate
Control and Port Egress Rate Control 2 registers macros with
MV88E6XXX_PORT_EGRESS_RATE_CTL1 and MV88E6XXX_PORT_EGRESS_RATE_CTL2.

Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.

Signed-off-by: default avatarVivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 81c6edb2

drivers/net/dsa/mv88e6xxx/chip.c

+2 −1
Original line number Diff line number Diff line
@@ -1897,7 +1897,8 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 
		return err;



	/* Egress rate control 2: disable egress rate control. */

	err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);

	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,

				   0x0000);

	if (err)

		return err;

drivers/net/dsa/mv88e6xxx/port.c

+4 −2
Original line number Diff line number Diff line
@@ -859,12 +859,14 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 


int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)

{

	return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0000);

	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,

				    0x0000);

}



int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)

{

	return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0001);

	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,

				    0x0001);

}



/* Offset 0x0C: Port ATU Control */

drivers/net/dsa/mv88e6xxx/port.h

+6 −2
Original line number Diff line number Diff line
@@ -177,8 +177,12 @@ 
#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR		0x0010

#define MV88E6095_PORT_CTL2_CPU_PORT_MASK		0x000f



#define PORT_RATE_CONTROL	0x09

#define PORT_RATE_CONTROL_2	0x0a

/* Offset 0x09: Egress Rate Control */

#define MV88E6XXX_PORT_EGRESS_RATE_CTL1		0x09



/* Offset 0x0A: Egress Rate Control 2 */

#define MV88E6XXX_PORT_EGRESS_RATE_CTL2		0x0a



#define PORT_ASSOC_VECTOR	0x0b

#define PORT_ASSOC_VECTOR_HOLD_AT_1		BIT(15)

#define PORT_ASSOC_VECTOR_INT_AGE_OUT		BIT(14)