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Commit 2c8672c1 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Fix initvals for freq 2484 



This is missing for AR9300, AR9580 and AR9340.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 40cc87de

drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h

+7 −0
Original line number Original line Diff line number Diff line
@@ -1738,4 +1738,11 @@ static const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = { 
	{0x00004044, 0x00000000},

	{0x00004044, 0x00000000},

};

};





static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = {

	/* Addr      allmodes  */

	{0x0000a398, 0x00000000},

	{0x0000a39c, 0x6f7f0301},

	{0x0000a3a0, 0xca9228ee},

};



#endif /* INITVALS_9003_2P2_H */
 
#endif /* INITVALS_9003_2P2_H */

drivers/net/wireless/ath/ath9k/ar9003_hw.c

+9 −3
Original line number Original line Diff line number Diff line
@@ -150,6 +150,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 




		INIT_INI_ARRAY(&ah->iniModesFastClock,

		INIT_INI_ARRAY(&ah->iniModesFastClock,

			       ar9340Modes_fast_clock_1p0);

			       ar9340Modes_fast_clock_1p0);

		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

			       ar9340_1p0_baseband_core_txfir_coeff_japan_2484);





		if (!ah->is_clk_25mhz)

		if (!ah->is_clk_25mhz)

			INIT_INI_ARRAY(&ah->iniAdditional,

			INIT_INI_ARRAY(&ah->iniAdditional,
@@ -336,6 +338,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 




		INIT_INI_ARRAY(&ah->iniModesFastClock,

		INIT_INI_ARRAY(&ah->iniModesFastClock,

			       ar9580_1p0_modes_fast_clock);

			       ar9580_1p0_modes_fast_clock);

		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

			       ar9580_1p0_baseband_core_txfir_coeff_japan_2484);

	} else if (AR_SREV_9565_11_OR_LATER(ah)) {

	} else if (AR_SREV_9565_11_OR_LATER(ah)) {

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],

			       ar9565_1p1_mac_core);

			       ar9565_1p1_mac_core);
@@ -452,6 +456,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 
		/* Fast clock modal settings */

		/* Fast clock modal settings */

		INIT_INI_ARRAY(&ah->iniModesFastClock,

		INIT_INI_ARRAY(&ah->iniModesFastClock,

			       ar9300Modes_fast_clock_2p2);

			       ar9300Modes_fast_clock_2p2);

		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

			       ar9300_2p2_baseband_core_txfir_coeff_japan_2484);

	}

	}

}

}

drivers/net/wireless/ath/ath9k/ar9340_initvals.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -28,6 +28,8 @@ 




#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2

#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2





#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484



static const u32 ar9340_1p0_radio_postamble[][5] = {

static const u32 ar9340_1p0_radio_postamble[][5] = {

	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */

	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */

	{0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},

	{0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},

drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -36,7 +36,7 @@ 




#define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2

#define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2





#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484

#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484





static const u32 ar9580_1p0_radio_postamble[][5] = {

static const u32 ar9580_1p0_radio_postamble[][5] = {

	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */

	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */