Merge "ARM: dts: msm: Add NPU QDSS related clocks for sm8150" (2c450d05) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sm8150-npu.dtsi

+26 −18

Original line number	Diff line number	Diff line
		@@ -24,7 +24,6 @@
		cache-slice-names = "npu";
		cache-slices = <&llcc 23>;
		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,
		<&clock_npucc NPU_CC_CAL_DP_CLK_SRC>,
		<&clock_npucc NPU_CC_XO_CLK>,
		<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,
		<&clock_npucc NPU_CC_BTO_CORE_CLK>,
		@@ -35,15 +34,16 @@
		<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,
		<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,
		<&clock_npucc NPU_CC_NPU_CORE_CLK>,
		<&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>,
		<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,
		<&clock_npucc NPU_CC_NPU_CPC_CLK>,
		<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,
		<&clock_npucc NPU_CC_PERF_CNT_CLK>,
		<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,
		<&clock_npucc NPU_CC_SLEEP_CLK>;
		<&clock_npucc NPU_CC_SLEEP_CLK>,
		<&clock_gcc GCC_NPU_AT_CLK>,
		<&clock_gcc GCC_NPU_TRIG_CLK>,
		<&clock_aop QDSS_CLK>;
		clock-names = "cal_dp_clk",
		"cal_dp_clk_src",
		"xo_clk",
		"armwic_core_clk",
		"bto_core_clk",
		@@ -54,13 +54,15 @@
		"npu_core_apb_clk",
		"npu_core_atb_clk",
		"npu_core_clk",
		"npu_core_clk_src",
		"npu_core_cti_clk",
		"npu_cpc_clk",
		"npu_cpc_timer_clk",
		"perf_cnt_clk",
		"qtimer_core_clk",
		"sleep_clk";
		"sleep_clk",
		"at_clk",
		"trig_clk",
		"qdss_clk";
		vdd-supply = <&npu_core_gdsc>;
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names ="vdd", "vdd_cx";
		@@ -77,7 +79,6 @@
		qcom,npu-pwrlevel@0 {
		reg = <0>;
		clk-freq = <9600000
		9600000
		19200000
		19200000
		19200000
		@@ -91,15 +92,16 @@
		19200000
		19200000
		19200000
		19200000
		9600000
		19200000
		0
		0
		0
		0>;
		};
		qcom,npu-pwrlevel@1 {
		reg = <1>;
		clk-freq = <300000000
		300000000
		19200000
		100000000
		19200000
		@@ -110,18 +112,19 @@
		19200000
		60000000
		100000000
		100000000
		37500000
		100000000
		19200000
		300000000
		19200000
		0
		0
		0
		0>;
		};
		qcom,npu-pwrlevel@2 {
		reg = <2>;
		clk-freq = <350000000
		350000000
		19200000
		150000000
		19200000
		@@ -132,18 +135,19 @@
		19200000
		120000000
		150000000
		150000000
		75000000
		150000000
		19200000
		350000000
		19200000
		0
		0
		0
		0>;
		};
		qcom,npu-pwrlevel@3 {
		reg = <3>;
		clk-freq = <400000000
		400000000
		19200000
		200000000
		19200000
		@@ -154,18 +158,19 @@
		19200000
		120000000
		200000000
		200000000
		75000000
		200000000
		19200000
		400000000
		19200000
		0
		0
		0
		0>;
		};
		qcom,npu-pwrlevel@4 {
		reg = <4>;
		clk-freq = <600000000
		600000000
		19200000
		300000000
		19200000
		@@ -176,18 +181,19 @@
		19200000
		240000000
		300000000
		300000000
		150000000
		300000000
		19200000
		600000000
		19200000
		0
		0
		0
		0>;
		};
		qcom,npu-pwrlevel@5 {
		reg = <5>;
		clk-freq = <715000000
		715000000
		19200000
		350000000
		19200000
		@@ -198,12 +204,14 @@
		19200000
		240000000
		350000000
		350000000
		150000000
		350000000
		19200000
		715000000
		19200000
		0
		0
		0
		0>;
		};
		};

drivers/media/platform/msm/npu/npu_common.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -67,7 +67,7 @@
		#define ROW_BYTES 16
		#define GROUP_BYTES 4

		#define NUM_TOTAL_CLKS 19
		#define NUM_TOTAL_CLKS 20
		#define NPU_MAX_REGULATOR_NUM 2
		#define NPU_MAX_DT_NAME_LEN 21
		#define NPU_MAX_PWRLEVELS 7

drivers/media/platform/msm/npu/npu_dev.c

+30 −41

Original line number	Diff line number	Diff line
		@@ -64,7 +64,6 @@ static ssize_t npu_store_pwr_state(struct device *dev,
		static void npu_suspend_devbw(struct npu_device *npu_dev);
		static void npu_resume_devbw(struct npu_device *npu_dev);
		static bool npu_is_post_clock(const char *clk_name);
		static bool npu_is_exclude_clock(const char *clk_name);
		static bool npu_is_exclude_rate_clock(const char *clk_name);
		static int npu_get_max_state(struct thermal_cooling_device *cdev,
		unsigned long *state);
		@@ -99,13 +98,14 @@ static void __exit npu_exit(void);
		* -------------------------------------------------------------------------
		*/
		static const char * const npu_clock_order[] = {
		"qdss_clk",
		"at_clk",
		"trig_clk",
		"armwic_core_clk",
		"cal_dp_clk_src",
		"cal_dp_clk",
		"cal_dp_cdc_clk",
		"conf_noc_ahb_clk",
		"comp_noc_axi_clk",
		"npu_core_clk_src",
		"npu_core_clk",
		"npu_core_cti_clk",
		"npu_core_apb_clk",
		@@ -125,19 +125,14 @@ static const char * const npu_post_clocks[] = {
		"npu_cpc_timer_clk"
		};

		static const char * const npu_exclude_clocks[] = {
		"npu_core_clk_src",
		"cal_dp_clk_src",
		"perf_cnt_clk",
		"npu_core_cti_clk",
		"npu_core_apb_clk",
		"npu_core_atb_clk"
		};

		static const char * const npu_exclude_rate_clocks[] = {
		"qdss_clk",
		"at_clk",
		"trig_clk",
		"sleep_clk",
		"xo_clk",
		"conf_noc_ahb_clk",
		"comp_noc_axi_clk",
		"npu_core_cti_clk",
		"npu_core_apb_clk",
		"npu_core_atb_clk",
		@@ -354,7 +349,6 @@ static int npu_set_power_level(struct npu_device *npu_dev)
		struct npu_pwrctrl *pwr = &npu_dev->pwrctrl;
		struct npu_pwrlevel *pwrlevel;
		int i, ret = 0;
		long clk_rate = 0;
		uint32_t pwr_level_to_set;

		if (!pwr->pwr_vote_num) {
		@@ -388,13 +382,12 @@ static int npu_set_power_level(struct npu_device *npu_dev)
		pr_debug("requested rate of clock [%s] to [%ld]\n",
		npu_dev->core_clks[i].clk_name, pwrlevel->clk_freq[i]);

		pr_debug("actual round clk rate [%ld]\n", clk_rate);

		ret = clk_set_rate(npu_dev->core_clks[i].clk, clk_rate);
		ret = clk_set_rate(npu_dev->core_clks[i].clk,
		pwrlevel->clk_freq[i]);
		if (ret) {
		pr_debug("clk_set_rate %s to %ld failed with %d\n",
		npu_dev->core_clks[i].clk_name,
		clk_rate, ret);
		pwrlevel->clk_freq[i], ret);
		break;
		}
		}
		@@ -491,20 +484,6 @@ static bool npu_is_post_clock(const char *clk_name)
		return ret;
		}

		static bool npu_is_exclude_clock(const char *clk_name)
		{
		int ret = false;
		int i;

		for (i = 0; i < ARRAY_SIZE(npu_exclude_clocks); i++) {
		if (!strcmp(clk_name, npu_exclude_clocks[i])) {
		ret = true;
		break;
		}
		}
		return ret;
		}

		static bool npu_is_exclude_rate_clock(const char *clk_name)
		{
		int ret = false;
		@@ -536,10 +515,7 @@ static int npu_enable_core_clocks(struct npu_device *npu_dev, bool post_pil)
		continue;
		}

		if (npu_is_exclude_clock(core_clks[i].clk_name))
		continue;

		pr_debug("enabling clock [%s]\n", core_clks[i].clk_name);
		pr_debug("enabling clock %s\n", core_clks[i].clk_name);

		rc = clk_prepare_enable(core_clks[i].clk);
		if (rc) {
		@@ -551,16 +527,31 @@ static int npu_enable_core_clocks(struct npu_device *npu_dev, bool post_pil)
		if (npu_is_exclude_rate_clock(core_clks[i].clk_name))
		continue;

		pr_debug("setting rate of clock [%s] to [%ld]\n",
		pr_debug("setting rate of clock %s to %ld\n",
		core_clks[i].clk_name, pwrlevel->clk_freq[i]);

		rc = clk_set_rate(core_clks[i].clk,
		pwrlevel->clk_freq[i]);
		/* not fatal error, keep using previous clk rate */
		if (rc) {
		pr_debug("clk_set_rate %s to %ld failed\n",
		pr_err("clk_set_rate %s to %ld failed\n",
		core_clks[i].clk_name,
		pwrlevel->clk_freq[i]);
		break;
		rc = 0;
		}
		}

		if (rc) {
		for (i--; i >= 0; i--) {
		if (post_pil) {
		if (!npu_is_post_clock(core_clks[i].clk_name))
		continue;
		} else {
		if (npu_is_post_clock(core_clks[i].clk_name))
		continue;
		}
		pr_debug("disabling clock %s\n", core_clks[i].clk_name);
		clk_disable_unprepare(core_clks[i].clk);
		}
		}

		@@ -573,14 +564,12 @@ static void npu_disable_core_clocks(struct npu_device *npu_dev)
		struct npu_clk *core_clks = npu_dev->core_clks;

		for (i = (npu_dev->core_clk_num)-1; i >= 0 ; i--) {
		if (npu_is_exclude_clock(core_clks[i].clk_name))
		continue;
		if (npu_dev->host_ctx.fw_state == FW_DISABLED) {
		if (npu_is_post_clock(npu_dev->core_clks[i].clk_name))
		continue;
		}

		pr_debug("disabling clock [%s]\n", core_clks[i].clk_name);
		pr_debug("disabling clock %s\n", core_clks[i].clk_name);
		clk_disable_unprepare(core_clks[i].clk);
		}
		}