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Commit 2baef134 authored Jun 21, 2018 by Harry Yang

power: smb5: Disable SMB thermal regulation



Disable SMB temp sensing/regulation for both SMB1355 and SMB1390.

SMB1390 has its own over-temp shutdown and has thermal balancing
SW to adjust PM/SMB charger current ratio using VBUS/VWLS.

SMB1355 has both CTM and thermal balance to regulate SMB ICHG.

Change-Id: I9fdedbb4055dc757187531d6aa0b5394c3916c1c
Signed-off-by: Harry Yang <harryy@codeaurora.org>

parent 3c388933

drivers/power/supply/qcom/qpnp-smb5.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -1607,6 +1607,15 @@ static int smb5_init_hw(struct smb5 *chip)
		return rc;
		}

		/* Disable SMB Temperature ADC INT */
		rc = smblib_masked_write(chg, MISC_THERMREG_SRC_CFG_REG,
		THERMREG_SMB_ADC_SRC_EN_BIT, 0);
		if (rc < 0) {
		dev_err(chg->dev, "Couldn't configure SMB thermal regulation rc=%d\n",
		rc);
		return rc;
		}

		/* Use SW based VBUS control, disable HW autonomous mode */
		rc = smblib_masked_write(chg, USBIN_OPTIONS_1_CFG_REG,
		HVDCP_AUTH_ALG_EN_CFG_BIT \| HVDCP_AUTONOMOUS_MODE_EN_CFG_BIT,

drivers/power/supply/qcom/smb5-reg.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -387,6 +387,9 @@ enum {
		#define AICL_RERUN_TIME_CFG_REG (MISC_BASE + 0x61)
		#define AICL_RERUN_TIME_12S_VAL 0x01

		#define MISC_THERMREG_SRC_CFG_REG (MISC_BASE + 0x70)
		#define THERMREG_SMB_ADC_SRC_EN_BIT BIT(5)

		#define MISC_SMB_CFG_REG (MISC_BASE + 0x90)
		#define SMB_EN_SEL_BIT BIT(4)
		#define CP_EN_POLARITY_CFG_BIT BIT(3)