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Commit 2b5e54e2 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
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ath9k: Add support for AR9462 2.1



Various parts of the HW code are applicable for
both v2.0 and v2.1.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent d567e4eb
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+4 −3
Original line number Original line Diff line number Diff line
@@ -3606,7 +3606,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
	 *   7:4 R/W  SWITCH_TABLE_COM_SPDT_WLAN_IDLE
	 *   7:4 R/W  SWITCH_TABLE_COM_SPDT_WLAN_IDLE
	 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
	 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
	 */
	 */
	if (AR_SREV_9462_20(ah) || AR_SREV_9565(ah)) {
	if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) {
		value = ar9003_switch_com_spdt_get(ah, is2ghz);
		value = ar9003_switch_com_spdt_get(ah, is2ghz);
		REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
		REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
				AR_SWITCH_TABLE_COM_SPDT_ALL, value);
				AR_SWITCH_TABLE_COM_SPDT_ALL, value);
@@ -4059,8 +4059,9 @@ static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah)
{
{
	u32 data, ko, kg;
	u32 data, ko, kg;


	if (!AR_SREV_9462_20(ah))
	if (!AR_SREV_9462_20_OR_LATER(ah))
		return;
		return;

	ar9300_otp_read_word(ah, 1, &data);
	ar9300_otp_read_word(ah, 1, &data);
	ko = data & 0xff;
	ko = data & 0xff;
	kg = (data >> 8) & 0xff;
	kg = (data >> 8) & 0xff;
@@ -4752,7 +4753,7 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah,
			      AR_PHY_TPC_19_ALPHA_THERM, temp_slope);
			      AR_PHY_TPC_19_ALPHA_THERM, temp_slope);
	}
	}


	if (AR_SREV_9462_20(ah))
	if (AR_SREV_9462_20_OR_LATER(ah))
		REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
		REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
			      AR_PHY_TPC_19_B1_ALPHA_THERM, temp_slope);
			      AR_PHY_TPC_19_B1_ALPHA_THERM, temp_slope);


+3 −3
Original line number Original line Diff line number Diff line
@@ -743,7 +743,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
		ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
		ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
		ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
		ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
		ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
		ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
		if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
		if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
			ar9003_hw_prog_ini(ah,
			ar9003_hw_prog_ini(ah,
					   &ah->ini_radio_post_sys2ant,
					   &ah->ini_radio_post_sys2ant,
					   modesIndex);
					   modesIndex);
@@ -754,7 +754,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
	 */
	 */
	REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
	REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);


	if (AR_SREV_9462_20(ah)) {
	if (AR_SREV_9462_20_OR_LATER(ah)) {
		/*
		/*
		 * CUS217 mix LNA mode.
		 * CUS217 mix LNA mode.
		 */
		 */
@@ -1512,7 +1512,7 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
	ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
	ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
	ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
	ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);


	if (AR_SREV_9462_20(ah))
	if (AR_SREV_9462_20_OR_LATER(ah))
		ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
		ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
				   modesIndex);
				   modesIndex);


+2 −2
Original line number Original line Diff line number Diff line
@@ -954,7 +954,7 @@
#define AR_PHY_TPC_5_B1         (AR_SM1_BASE + 0x208)
#define AR_PHY_TPC_5_B1         (AR_SM1_BASE + 0x208)
#define AR_PHY_TPC_6_B1         (AR_SM1_BASE + 0x20c)
#define AR_PHY_TPC_6_B1         (AR_SM1_BASE + 0x20c)
#define AR_PHY_TPC_11_B1        (AR_SM1_BASE + 0x220)
#define AR_PHY_TPC_11_B1        (AR_SM1_BASE + 0x220)
#define AR_PHY_PDADC_TAB_1	(AR_SM1_BASE + (AR_SREV_AR9462(ah) ? \
#define AR_PHY_PDADC_TAB_1	(AR_SM1_BASE + (AR_SREV_9462_20_OR_LATER(ah) ? \
					0x280 : 0x240))
					0x280 : 0x240))
#define AR_PHY_TPC_19_B1	(AR_SM1_BASE + 0x240)
#define AR_PHY_TPC_19_B1	(AR_SM1_BASE + 0x240)
#define AR_PHY_TPC_19_B1_ALPHA_THERM		0xff
#define AR_PHY_TPC_19_B1_ALPHA_THERM		0xff
@@ -1048,7 +1048,7 @@
#define AR_GLB_GPIO_CONTROL	(AR_GLB_BASE)
#define AR_GLB_GPIO_CONTROL	(AR_GLB_BASE)
#define AR_PHY_GLB_CONTROL	(AR_GLB_BASE + 0x44)
#define AR_PHY_GLB_CONTROL	(AR_GLB_BASE + 0x44)
#define AR_GLB_SCRATCH(_ah)	(AR_GLB_BASE + \
#define AR_GLB_SCRATCH(_ah)	(AR_GLB_BASE + \
					(AR_SREV_9462_20(_ah) ? 0x4c : 0x50))
					(AR_SREV_9462_20_OR_LATER(_ah) ? 0x4c : 0x50))
#define AR_GLB_STATUS		(AR_GLB_BASE + 0x48)
#define AR_GLB_STATUS		(AR_GLB_BASE + 0x48)


/*
/*
+1 −1
Original line number Original line Diff line number Diff line
@@ -2599,7 +2599,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
		if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
		if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
			pCap->hw_caps |= ATH9K_HW_CAP_MCI;
			pCap->hw_caps |= ATH9K_HW_CAP_MCI;


		if (AR_SREV_9462_20(ah))
		if (AR_SREV_9462_20_OR_LATER(ah))
			pCap->hw_caps |= ATH9K_HW_CAP_RTT;
			pCap->hw_caps |= ATH9K_HW_CAP_RTT;
	}
	}