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Commit 29adec9b authored by Sujeev Dias's avatar Sujeev Dias Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: reconfigure sdx50 memory access based on AC policy 



For sm8150-sdx50 access control policy is SMMU S2 only
configuration with a dedicated memory pool. Configuring
MHI nodes to reflect AC configuration.

CRs-Fixed: 2280647
Change-Id: I869c6b79661611d2ac9754b96b4012b082117f07
Signed-off-by: default avatarSujeev Dias <sdias@codeaurora.org>
parent 952512e3

arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi

+23 −10
Original line number Diff line number Diff line
@@ -45,8 +45,23 @@ 
&mhi_0 {

	esoc-names = "mdm";

	esoc-0 = <&mdm3>;

	qcom,smmu-cfg = <0x1d>;

	qcom,addr-win = <0x0 0x20000000 0x0 0x3fffffff>;

	qcom,smmu-cfg = <0>;

	memory-region = <&mhi_mem>;

	mhi,use-bb;

	mhi,buffer-len = <0x8000>;

	qcom,addr-win = <0x0 0xa0000000 0x0 0xa4bfffff>;



	mhi_chan@1 {

		mhi,num-elements = <32>;

	};



	mhi_chan@11 {

		mhi,num-elements = <32>;

	};



	mhi_chan@21 {

		mhi,num-elements = <32>;

	};

};



&tlmm {
@@ -67,8 +82,6 @@ 
};



&pcie1 {

	dma-coherent;



	pinctrl-0 = <&pcie1_clkreq_default

		&pcie1_perst_default

		&pcie1_sdx50m_wake_default>;
@@ -77,8 +90,6 @@ 
&soc {

	imp: qcom,ipa-mhi-proxy {

		compatible = "qcom,ipa-mhi-proxy";

		qcom,ctrl-iova = <0x00010000 0x0FFF0000>;

		qcom,data-iova = <0x10000000 0x0FFFFFFF>;

		qcom,mhi-chdb-base = <0x40300300>;

		qcom,mhi-erdb-base = <0x40300700>;

	};
@@ -97,9 +108,11 @@ 
		reg = <0x0 0xa1000000 0x0 0x02c00000>;

	};



	pil_pcie_mem: pil_pcie_mem_region@a3c00000 {

		compatible = "removed-dma-pool";

	mhi_mem: mhi_region {

		 compatible = "shared-dma-pool";

		 alloc-ranges = <0x0 0xa3c00000 0x0 0x01000000>;

		 alignment = <0x0 0x400000>;

		 size = <0x0 0x01000000>;

		 no-map;

		reg = <0x0 0xa3c00000 0x0 0x01000000>;

	};

};