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Commit 29869ad4 authored by Jonghwan Choi's avatar Jonghwan Choi Committed by Kukjin Kim
Browse files

ARM: EXYNOS: cleanup unused code related to GPS 



Signed-off-by: default avatarJonghwan Choi <jhbird.choi@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent fea7a08a

arch/arm/mach-exynos/clock-exynos5.c

+0 −9
Original line number Original line Diff line number Diff line
@@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable) 
	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);

	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);

}

}





static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);

}



static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)

static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)

{

{

	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);

	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -671,10 +666,6 @@ static struct clk exynos5_init_clocks_off[] = { 
		.name		= "usbotg",

		.name		= "usbotg",

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 7),

		.ctrlbit	= (1 << 7),

	}, {

		.name		= "gps",

		.enable		= exynos5_clk_ip_gps_ctrl,

		.ctrlbit	= ((1 << 3) | (1 << 2) | (1 << 0)),

	}, {

	}, {

		.name		= "nfcon",

		.name		= "nfcon",

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.enable		= exynos5_clk_ip_fsys_ctrl,

arch/arm/mach-exynos/include/mach/map.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -131,7 +131,6 @@ 
#define EXYNOS5_PA_SYSMMU_JPEG		0x11F20000

#define EXYNOS5_PA_SYSMMU_JPEG		0x11F20000

#define EXYNOS5_PA_SYSMMU_IOP		0x12360000

#define EXYNOS5_PA_SYSMMU_IOP		0x12360000

#define EXYNOS5_PA_SYSMMU_RTIC		0x12370000

#define EXYNOS5_PA_SYSMMU_RTIC		0x12370000

#define EXYNOS5_PA_SYSMMU_GPS		0x12630000

#define EXYNOS5_PA_SYSMMU_ISP		0x13260000

#define EXYNOS5_PA_SYSMMU_ISP		0x13260000

#define EXYNOS5_PA_SYSMMU_DRC		0x12370000

#define EXYNOS5_PA_SYSMMU_DRC		0x12370000

#define EXYNOS5_PA_SYSMMU_SCALERC	0x13280000

#define EXYNOS5_PA_SYSMMU_SCALERC	0x13280000