Loading arch/arm64/boot/dts/qcom/sm8150-v2.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -924,6 +924,18 @@ < 2841600 1612000000 >; }; &cpu7_cpu_l3_latmon { qcom,core-dev-table = < 300000 300000000 >, < 825600 614400000 >, < 1171200 806400000 >, < 1401600 998400000 >, < 1708800 1267200000 >, < 2016000 1344000000 >, < 2419200 1536000000 >, < 2841600 1612000000 >; }; &cpu0_cpu_llcc_latmon { qcom,core-dev-table = < 300000 MHZ_TO_MBPS( 150, 16) >, Loading arch/arm64/boot/dts/qcom/sm8150.dtsi +23 −2 Original line number Diff line number Diff line Loading @@ -1144,7 +1144,7 @@ cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,cpulist = <&CPU4 &CPU5 &CPU6>; qcom,target-dev = <&cpu4_cpu_l3_lat>; qcom,cachemiss-ev = <0x17>; qcom,core-dev-table = Loading @@ -1156,6 +1156,27 @@ < 2016000 1344000000 >; }; cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { compatible = "devfreq-simple-dev"; clock-names = "devfreq_clk"; clocks = <&clock_cpucc L3_CLUSTER2_VOTE_CLK>; governor = "performance"; }; cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU7>; qcom,target-dev = <&cpu7_cpu_l3_lat>; qcom,cachemiss-ev = <0x17>; qcom,core-dev-table = < 300000 300000000 >, < 768000 576000000 >, < 1152000 768000000 >, < 1344000 960000000 >, < 1689600 1228800000 >, < 2016000 1344000000 >; }; cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { compatible = "qcom,devbw"; governor = "performance"; Loading Loading @@ -1513,7 +1534,7 @@ reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base", "osm_perfpcl_base"; l3-devs = <&cpu0_cpu_l3_lat &cpu4_cpu_l3_lat &cdsp_cdsp_l3_lat &msm_gpu>; &msm_gpu &cpu7_cpu_l3_lat>; #clock-cells = <1>; }; Loading drivers/devfreq/governor_memlat.c +1 −1 Original line number Diff line number Diff line Loading @@ -323,7 +323,7 @@ static int devfreq_memlat_get_freq(struct devfreq *df, return 0; } gov_attr(ratio_ceil, 1U, 10000U); gov_attr(ratio_ceil, 1U, 20000U); gov_attr(stall_floor, 0U, 100U); static struct attribute *memlat_dev_attr[] = { Loading Loading
arch/arm64/boot/dts/qcom/sm8150-v2.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -924,6 +924,18 @@ < 2841600 1612000000 >; }; &cpu7_cpu_l3_latmon { qcom,core-dev-table = < 300000 300000000 >, < 825600 614400000 >, < 1171200 806400000 >, < 1401600 998400000 >, < 1708800 1267200000 >, < 2016000 1344000000 >, < 2419200 1536000000 >, < 2841600 1612000000 >; }; &cpu0_cpu_llcc_latmon { qcom,core-dev-table = < 300000 MHZ_TO_MBPS( 150, 16) >, Loading
arch/arm64/boot/dts/qcom/sm8150.dtsi +23 −2 Original line number Diff line number Diff line Loading @@ -1144,7 +1144,7 @@ cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,cpulist = <&CPU4 &CPU5 &CPU6>; qcom,target-dev = <&cpu4_cpu_l3_lat>; qcom,cachemiss-ev = <0x17>; qcom,core-dev-table = Loading @@ -1156,6 +1156,27 @@ < 2016000 1344000000 >; }; cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { compatible = "devfreq-simple-dev"; clock-names = "devfreq_clk"; clocks = <&clock_cpucc L3_CLUSTER2_VOTE_CLK>; governor = "performance"; }; cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU7>; qcom,target-dev = <&cpu7_cpu_l3_lat>; qcom,cachemiss-ev = <0x17>; qcom,core-dev-table = < 300000 300000000 >, < 768000 576000000 >, < 1152000 768000000 >, < 1344000 960000000 >, < 1689600 1228800000 >, < 2016000 1344000000 >; }; cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { compatible = "qcom,devbw"; governor = "performance"; Loading Loading @@ -1513,7 +1534,7 @@ reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base", "osm_perfpcl_base"; l3-devs = <&cpu0_cpu_l3_lat &cpu4_cpu_l3_lat &cdsp_cdsp_l3_lat &msm_gpu>; &msm_gpu &cpu7_cpu_l3_lat>; #clock-cells = <1>; }; Loading
drivers/devfreq/governor_memlat.c +1 −1 Original line number Diff line number Diff line Loading @@ -323,7 +323,7 @@ static int devfreq_memlat_get_freq(struct devfreq *df, return 0; } gov_attr(ratio_ceil, 1U, 10000U); gov_attr(ratio_ceil, 1U, 20000U); gov_attr(stall_floor, 0U, 100U); static struct attribute *memlat_dev_attr[] = { Loading