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Commit 2910f145 authored by Paul Walmsley's avatar Paul Walmsley
Browse files

Merge tag 'omap-cleanup-b-for-3.7' into test_v3.6-rc6_ocb3.7_cff3.7_odaf3.7 

smatch and string-wrapping cleanups for the OMAP subarch code.

These changes fix some of the more meaningful warnings that smatch
returns for the OMAP subarch code, and unwraps strings that are
wrapped at the 80-column boundary, to conform with the current
practice.

Basic build, boot, and PM logs are available here:

http://www.pwsan.com/omap/testlogs/warnings_a_cleanup_3.7/20120912025927/
parents 5698bd75 7852ec05

arch/arm/mach-omap1/board-htcherald.c

+1 −2
Original line number Diff line number Diff line
@@ -476,8 +476,7 @@ static void __init htcherald_lcd_init(void) 
				break;

		}

		if (!tries)

			printk(KERN_WARNING "Timeout waiting for end of frame "

			       "-- LCD may not be available\n");

			pr_err("Timeout waiting for end of frame -- LCD may not be available\n");



		/* turn off DMA */

		reg = omap_readw(OMAP_DMA_LCD_CCR);

arch/arm/mach-omap1/clock.c

+2 −2
Original line number Diff line number Diff line
@@ -587,8 +587,8 @@ void omap1_clk_disable_unused(struct clk *clk) 
	/* Clocks in the DSP domain need api_ck. Just assume bootloader

	 * has not enabled any DSP clocks */

	if (clk->enable_reg == DSP_IDLECT2) {

		printk(KERN_INFO "Skipping reset check for DSP domain "

		       "clock \"%s\"\n", clk->name);

		pr_info("Skipping reset check for DSP domain clock \"%s\"\n",

			clk->name);

		return;

	}

arch/arm/mach-omap1/clock_data.c

+6 −7
Original line number Diff line number Diff line
@@ -776,8 +776,7 @@ static struct clk_functions omap1_clk_functions = { 


static void __init omap1_show_rates(void)

{

	pr_notice("Clocking rate (xtal/DPLL1/MPU): "

			"%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",

	pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",

		  ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,

		  ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,

		  arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
@@ -848,8 +847,8 @@ int __init omap1_clk_init(void) 
	if (cpu_is_omap16xx() && crystal_type == 2)

		ck_ref.rate = 19200000;



	pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "

		"0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),

	pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",

		omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),

		omap_readw(ARM_CKCTL));



	/* We want to be in syncronous scalable mode */

arch/arm/mach-omap1/dma.c

+3 −2
Original line number Diff line number Diff line
@@ -330,8 +330,9 @@ static int __init omap1_system_dma_init(void) 
	d->chan = kzalloc(sizeof(struct omap_dma_lch) *

					(d->lch_count), GFP_KERNEL);

	if (!d->chan) {

		dev_err(&pdev->dev, "%s: Memory allocation failed"

					"for d->chan!!!\n", __func__);

		dev_err(&pdev->dev,

			"%s: Memory allocation failed for d->chan!\n",

			__func__);

		goto exit_release_d;

	}

arch/arm/mach-omap1/lcd_dma.c

+2 −4
Original line number Diff line number Diff line
@@ -113,8 +113,7 @@ EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror); 
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)

{

	if (cpu_is_omap15xx()) {

		printk(KERN_ERR "DMA virtual resolution is not supported "

				"in 1510 mode\n");

		pr_err("DMA virtual resolution is not supported in 1510 mode\n");

		BUG();

	}

	lcd_dma.vxres = vxres;
@@ -437,8 +436,7 @@ static int __init omap_init_lcd_dma(void) 
	r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,

			"LCD DMA", NULL);

	if (r != 0)

		printk(KERN_ERR "unable to request IRQ for LCD DMA "

			       "(error %d)\n", r);

		pr_err("unable to request IRQ for LCD DMA (error %d)\n", r);



	return r;

}