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Commit 29081787 authored by Mulu He's avatar Mulu He Committed by Gerrit - the friendly Code Review server
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ARM: dts: coresight: Enable etm1~etm7 for SDM855 



Enable etm1~etm7 for SDM855.

Change-Id: I01c4544015889f35e427d1f4a4ecff8d738f312e
Signed-off-by: default avatarMulu He <muluhe@codeaurora.org>
parent 66ad6f80

arch/arm64/boot/dts/qcom/sdm855-coresight.dtsi

+0 −7
Original line number Diff line number Diff line
@@ -2230,7 +2230,6 @@ 
		cpu = <&CPU1>;



		coresight-name = "coresight-etm1";

		status = "disabled";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -2250,7 +2249,6 @@ 
		cpu = <&CPU2>;



		coresight-name = "coresight-etm2";

		status = "disabled";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -2270,7 +2268,6 @@ 
		cpu = <&CPU3>;



		coresight-name = "coresight-etm3";

		status = "disabled";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -2290,7 +2287,6 @@ 
		cpu = <&CPU4>;



		coresight-name = "coresight-etm4";

		status = "disabled";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -2310,7 +2306,6 @@ 
		cpu = <&CPU5>;



		coresight-name = "coresight-etm5";

		status = "disabled";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -2330,7 +2325,6 @@ 
		cpu = <&CPU6>;



		coresight-name = "coresight-etm6";

		status = "disabled";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -2350,7 +2344,6 @@ 
		cpu = <&CPU7>;



		coresight-name = "coresight-etm7";

		status = "disabled";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";