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Commit 286e4a60 authored by Archana Sathyakumar's avatar Archana Sathyakumar Committed by Lina Iyer
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drivers: irqchip: pdc: Add QTI SOC interrupt controller 



Implement QTI SOC interrupt controller for configuring interrupts to
wakeup APSS from system sleep. Use hierarchical interrupt domain
framework as the arch-extension are no longer supported.

This is a snapshot as of commit 741a37a6166a ("drivers: irqchip: pdc:
Add QTI SOC interrupt controller").

Change-Id: I8a6ad64ac76ae1758dc3da84abad5d67f92106ab
Signed-off-by: default avatarArchana Sathyakumar <asathyak@codeaurora.org>
Signed-off-by: default avatarMahesh Sivasubramanian <msivasub@codeaurora.org>
parent bf5d008c

Documentation/devicetree/bindings/interrupt-controller/qti,pdc.txt

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QTI PDC interrupt controller



PDC is QTI's platform parent interrupt controller that serves as wakeup source.



Newer QTI SOCs are replacing MPM (MSM sleep Power Manager) with PDC (Power

Domain Controller) to manage subsystem wakeups and resources during sleep.

This driver marks the wakeup interrupts in APSS PDC such that it monitors the

interrupts when the system is asleep, wakes up the APSS when one of these

interrupts occur and replays it to the subsystem interrupt controller after it

becomes operational.



Earlier MPM architecture used arch-extension of GIC interrupt

controller to mark enabled wake-up interrupts and monitor these when the

system goes to sleep. Since the arch-extensions are no-longer available

on newer kernel versions, this driver is implemented as hierarchical irq

domain.  GIC is parent interrupt controller at the highest level.

Platform interrupt controller PDC is next in hierarchy, followed by others.

This driver only configures the interrupts, does not handle them.



PDC interrupt configuration involves programming of 2 set of registers:

IRQ_ENABLE_BANK    - Enable the irq

IRQ_i_CFG          - Configure the interrupt i



Properties:



- compatible:

	Usage: required

	Value type: <string>

	Definition: Should contain "qcom,pdc-<target>"



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: Specifies the base physical address for PDC hardware

			block for DRV2.



- interrupt-cells:

	Usage: required

	Value type: <u32>

	Definition: Specifies the number of cells needed to encode an interrupt source.

			Value must be 3.

			The encoding of these cells are same as described in

			Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt



- interrupt-parent:

	Usage: required

	Value type: <phandle>

	Definition: Specifies the interrupt parent necessary for hierarchical domain to operate.



- interrupt-controller:

	Usage: required

	Value type: <bool>

	Definition: Identifies the node as an interrupt controller.



Example:



pdcgic: interrupt-controller@0xb220000{

	compatible = "qcom,pdc-sdm845";

	reg = <0xb220000 0x30000>;

	#interrupt-cells = <3>;

	interrupt-parent = <&intc>;

	interrupt-controller;

};

drivers/irqchip/Kconfig

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@@ -341,3 +341,5 @@ config IRQ_UNIPHIER_AIDET 
	select IRQ_DOMAIN_HIERARCHY

	help

	  Support for the UniPhier AIDET (ARM Interrupt Detector).



source "drivers/irqchip/qcom/Kconfig"

drivers/irqchip/Makefile

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@@ -81,3 +81,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o 
obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o

obj-$(CONFIG_QCOM_IRQ_COMBINER)		+= qcom-irq-combiner.o

obj-$(CONFIG_IRQ_UNIPHIER_AIDET)	+= irq-uniphier-aidet.o

obj-$(CONFIG_QTI_PDC)			+= qcom/

drivers/irqchip/qcom/Kconfig

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config QTI_PDC

        bool "QTI PDC"

        depends on ARCH_QCOM

	select IRQ_DOMAIN

	select IRQ_DOMAIN_HIERARCHY

        help

          QTI Power Domain Controller driver to manage and configure wakeup

          IRQs

drivers/irqchip/qcom/Makefile

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obj-$(CONFIG_QTI_PDC)			+= pdc.o