Loading arch/arm64/boot/dts/qcom/sm8150-v2.dtsi +137 −0 Original line number Diff line number Diff line Loading @@ -22,6 +22,17 @@ /delete-node/ &apps_smmu; /delete-node/ &kgsl_smmu; &mdss_rotator { smmu_rot_unsec: qcom,smmu_rot_unsec_cb { compatible = "qcom,smmu_sde_rot_unsec"; iommus = <&apps_smmu 0x2040 0x0>; }; smmu_rot_sec: qcom,smmu_rot_sec_cb { compatible = "qcom,smmu_sde_rot_sec"; iommus = <&apps_smmu 0x2041 0x0>; }; }; &clock_gcc { compatible = "qcom,gcc-sm8150-v2", "syscon"; }; Loading Loading @@ -405,3 +416,129 @@ }; }; }; /* NPU overrides */ &msm_npu { qcom,npu-pwrlevels { #address-cells = <1>; #size-cells = <0>; compatible = "qcom,npu-pwrlevels"; initial-pwrlevel = <3>; qcom,npu-pwrlevel@0 { reg = <0>; clk-freq = <300000000 19200000 100000000 19200000 19200000 300000000 150000000 19200000 19200000 60000000 100000000 37500000 100000000 19200000 300000000 19200000 0 0 0 0>; }; qcom,npu-pwrlevel@1 { reg = <1>; clk-freq = <400000000 19200000 150000000 19200000 19200000 400000000 200000000 37500000 19200000 120000000 150000000 75000000 150000000 19200000 400000000 19200000 0 0 0 0>; }; qcom,npu-pwrlevel@2 { reg = <2>; clk-freq = <487000000 19200000 200000000 19200000 19200000 487000000 300000000 37500000 19200000 240000000 200000000 150000000 200000000 19200000 487000000 19200000 0 0 0 0>; }; qcom,npu-pwrlevel@3 { reg = <3>; clk-freq = <773000000 19200000 300000000 19200000 19200000 773000000 403000000 75000000 19200000 240000000 300000000 150000000 300000000 19200000 773000000 19200000 0 0 0 0>; }; qcom,npu-pwrlevel@4 { reg = <4>; clk-freq = <908000000 19200000 400000000 19200000 19200000 908000000 533000000 75000000 19200000 300000000 400000000 150000000 400000000 19200000 908000000 19200000 0 0 0 0>; }; /delete-node/ qcom,npu-pwrlevel@5; }; }; Loading
arch/arm64/boot/dts/qcom/sm8150-v2.dtsi +137 −0 Original line number Diff line number Diff line Loading @@ -22,6 +22,17 @@ /delete-node/ &apps_smmu; /delete-node/ &kgsl_smmu; &mdss_rotator { smmu_rot_unsec: qcom,smmu_rot_unsec_cb { compatible = "qcom,smmu_sde_rot_unsec"; iommus = <&apps_smmu 0x2040 0x0>; }; smmu_rot_sec: qcom,smmu_rot_sec_cb { compatible = "qcom,smmu_sde_rot_sec"; iommus = <&apps_smmu 0x2041 0x0>; }; }; &clock_gcc { compatible = "qcom,gcc-sm8150-v2", "syscon"; }; Loading Loading @@ -405,3 +416,129 @@ }; }; }; /* NPU overrides */ &msm_npu { qcom,npu-pwrlevels { #address-cells = <1>; #size-cells = <0>; compatible = "qcom,npu-pwrlevels"; initial-pwrlevel = <3>; qcom,npu-pwrlevel@0 { reg = <0>; clk-freq = <300000000 19200000 100000000 19200000 19200000 300000000 150000000 19200000 19200000 60000000 100000000 37500000 100000000 19200000 300000000 19200000 0 0 0 0>; }; qcom,npu-pwrlevel@1 { reg = <1>; clk-freq = <400000000 19200000 150000000 19200000 19200000 400000000 200000000 37500000 19200000 120000000 150000000 75000000 150000000 19200000 400000000 19200000 0 0 0 0>; }; qcom,npu-pwrlevel@2 { reg = <2>; clk-freq = <487000000 19200000 200000000 19200000 19200000 487000000 300000000 37500000 19200000 240000000 200000000 150000000 200000000 19200000 487000000 19200000 0 0 0 0>; }; qcom,npu-pwrlevel@3 { reg = <3>; clk-freq = <773000000 19200000 300000000 19200000 19200000 773000000 403000000 75000000 19200000 240000000 300000000 150000000 300000000 19200000 773000000 19200000 0 0 0 0>; }; qcom,npu-pwrlevel@4 { reg = <4>; clk-freq = <908000000 19200000 400000000 19200000 19200000 908000000 533000000 75000000 19200000 300000000 400000000 150000000 400000000 19200000 908000000 19200000 0 0 0 0>; }; /delete-node/ qcom,npu-pwrlevel@5; }; };
