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Commit 282815bf authored by Kyle Piefer's avatar Kyle Piefer
Browse files

msm: kgsl: Add support for Adaptive Clock Distribution 



Adaptive Clock Distribution (ACD) is a power feature that
mitigates voltage droops. ACD involves interactions
between the host, the GMU, and the AOP.

Change-Id: Ibffa62a0858ca9dabac4d5b382ad2b8a3167789e
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent a84db540

Documentation/devicetree/bindings/gpu/adreno-pwrlevels.txt

+6 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. GPU powerlevels 


Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins)

can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a

voltage, bus, and bandwitdh level.

voltage, bus, bandwidth level, and a DVM value.



- qcom,gpu-pwrlevel-bins:	Contains one or more qcom,gpu-pwrlevels sets
@@ -28,3 +28,8 @@ Properties: 
				settings)

- qcom,bus-min			Minimum bus level to set for the power level

- qcom,bus-max			maximum bus level to set for the power level

- qcom,dvm-val:			Value that is used as a register setting for

				the ACD power feature. It helps determine the

				threshold for when ACD activates. 0xFFFFFFFF

				is the default value, and the setting where

				ACD will never activate.

drivers/gpu/msm/adreno.c

+4 −0
Original line number Diff line number Diff line
@@ -965,6 +965,10 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev, 
		if (of_property_read_u32(child, "qcom,bus-max",

			&level->bus_max))

			level->bus_max = level->bus_freq;



		if (of_property_read_u32(child, "qcom,dvm-val",

				&level->acd_dvm_val))

			level->acd_dvm_val = 0xFFFFFFFF;

	}



	return 0;

drivers/gpu/msm/adreno.h

+6 −0
Original line number Diff line number Diff line
@@ -123,6 +123,11 @@ 
#define ADRENO_MIN_VOLT BIT(15)

/* The core supports IO-coherent memory */

#define ADRENO_IOCOHERENT BIT(16)

/*

 * The GMU supports Adaptive Clock Distribution (ACD)

 * for droop mitigation

 */

#define ADRENO_ACD BIT(17)



/*

 * Adreno GPU quirks - control bits for various workarounds
@@ -233,6 +238,7 @@ enum adreno_gpurev { 
#define ADRENO_LM_CTRL      2

#define ADRENO_HWCG_CTRL    3

#define ADRENO_THROTTLING_CTRL 4

#define ADRENO_ACD_CTRL 5



/* VBIF,  GBIF halt request and ack mask */

#define GBIF_HALT_REQUEST       0x1E0

drivers/gpu/msm/adreno_a6xx_gmu.c

+0 −6
Original line number Diff line number Diff line
@@ -301,12 +301,6 @@ static void a6xx_gmu_power_config(struct kgsl_device *device) 
		break;

	}



	/* ACD feature enablement */

	if (ADRENO_FEATURE(adreno_dev, ADRENO_LM) &&

		test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))

		gmu_core_regrmw(device, A6XX_GMU_BOOT_KMD_LM_HANDSHAKE, 0,

				BIT(10));



	/* Enable RPMh GPU client */

	if (ADRENO_FEATURE(adreno_dev, ADRENO_RPMH))

		gmu_core_regrmw(device, A6XX_GMU_RPMH_CTRL, 0,

drivers/gpu/msm/adreno_sysfs.c

+17 −1
Original line number Diff line number Diff line
@@ -312,6 +312,21 @@ static unsigned int _preempt_count_show(struct adreno_device *adreno_dev) 
	return preempt->count;

}



static unsigned int _acd_show(struct adreno_device *adreno_dev)

{

	return test_bit(ADRENO_ACD_CTRL, &adreno_dev->pwrctrl_flag);

}



static int _acd_store(struct adreno_device *adreno_dev, unsigned int val)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	if (test_bit(ADRENO_ACD_CTRL, &adreno_dev->pwrctrl_flag) == val)

		return 0;



	return gmu_core_acd_set(device, val);

}



static ssize_t _sysfs_store_u32(struct device *dev,

		struct device_attribute *attr,

		const char *buf, size_t count)
@@ -416,7 +431,7 @@ static ADRENO_SYSFS_BOOL(hwcg); 
static ADRENO_SYSFS_BOOL(throttling);

static ADRENO_SYSFS_BOOL(ifpc);

static ADRENO_SYSFS_RO_U32(ifpc_count);



static ADRENO_SYSFS_BOOL(acd);





static const struct device_attribute *_attr_list[] = {
@@ -439,6 +454,7 @@ static const struct device_attribute *_attr_list[] = { 
	&adreno_attr_ifpc.attr,

	&adreno_attr_ifpc_count.attr,

	&adreno_attr_preempt_count.attr,

	&adreno_attr_acd.attr,

	NULL,

};