Loading arch/arm64/boot/dts/qcom/sm6150-usb.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -163,7 +163,7 @@ /* Primary USB port related QMP USB PHY */ usb_qmp_phy: ssphy@88e6000 { compatible = "qcom,usb-ssphy-qmp-v2"; compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; reg = <0x88e6000 0x1000>; reg-names = "qmp_phy_base"; Loading Loading @@ -297,9 +297,9 @@ clock-names = "aux_clk", "pipe_clk", "ref_clk_src", "ref_clk", "com_aux_clk", "cfg_ahb_clk"; resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, resets = <&clock_gcc GCC_USB3_PHY_PRIM_SP0_BCR>, <&clock_gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; reset-names = "phy_phy_reset", "phy_reset"; reset-names = "phy_reset", "phy_phy_reset"; }; usb_audio_qmi_dev { Loading Loading
arch/arm64/boot/dts/qcom/sm6150-usb.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -163,7 +163,7 @@ /* Primary USB port related QMP USB PHY */ usb_qmp_phy: ssphy@88e6000 { compatible = "qcom,usb-ssphy-qmp-v2"; compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; reg = <0x88e6000 0x1000>; reg-names = "qmp_phy_base"; Loading Loading @@ -297,9 +297,9 @@ clock-names = "aux_clk", "pipe_clk", "ref_clk_src", "ref_clk", "com_aux_clk", "cfg_ahb_clk"; resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, resets = <&clock_gcc GCC_USB3_PHY_PRIM_SP0_BCR>, <&clock_gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; reset-names = "phy_phy_reset", "phy_reset"; reset-names = "phy_reset", "phy_phy_reset"; }; usb_audio_qmi_dev { Loading