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Commit 277e36c2 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add GPU speed bin support for Trinket"

parents a84ca779 963c17c2

arch/arm64/boot/dts/qcom/trinket-gpu.dtsi

+255 −71
Original line number Diff line number Diff line
@@ -51,8 +51,10 @@ 
		status = "ok";



		reg = <0x5900000 0x90000>,

			<0x5961000 0x800>;

		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc";

			<0x5961000 0x800>,

			<0x1b40000 0x6fff>;

		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc",

				"qfprom_memory";



		interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "kgsl_3d0_irq";
@@ -124,6 +126,8 @@ 
		/* Context aware jump target power level */

		qcom,ca-target-pwrlevel = <5>;



		qcom,gpu-speed-bin = <0x6004 0x1fe00000 21>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells = <1>;
@@ -156,12 +160,108 @@ 
			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

		/*

		 * Speed-bin zero is default speed bin.

		 * For rest of the speed bins, speed-bin value

		 * is calulated as FMAX/4.8 MHz round up to zero

		 * decimal places.

		 */

		qcom,gpu-pwrlevel-bins {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible="qcom,gpu-pwrlevel-bins";



			qcom,gpu-pwrlevels-0 {

				#address-cells = <1>;

				#size-cells = <0>;



				qcom,speed-bin = <0>;



				qcom,initial-pwrlevel = <6>;

				qcom,ca-target-pwrlevel = <5>;



				/* TURBO_L1 */

				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <980000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <10>;

					qcom,bus-max = <11>;

				};



				/* TURBO */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <900000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <9>;

					qcom,bus-max = <11>;

				};



				/* NOM_L1 */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <820000000>;

					qcom,bus-freq = <10>;

					qcom,bus-min = <9>;

					qcom,bus-max = <11>;

				};



				/* NOM */

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <745000000>;

					qcom,bus-freq = <9>;

					qcom,bus-min = <8>;

					qcom,bus-max = <10>;

				};



				/* SVS_L1 */

				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <600000000>;

					qcom,bus-freq = <8>;

					qcom,bus-min = <7>;

					qcom,bus-max = <9>;

				};



				/* SVS */

				qcom,gpu-pwrlevel@5 {

					reg = <5>;

					qcom,gpu-freq = <465000000>;

					qcom,bus-freq = <7>;

					qcom,bus-min = <5>;

					qcom,bus-max = <8>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@6 {

					reg = <6>;

					qcom,gpu-freq = <320000000>;

					qcom,bus-freq = <4>;

					qcom,bus-min = <3>;

					qcom,bus-max = <5>;

				};



				/* XO */

				qcom,gpu-pwrlevel@7 {

					reg = <7>;

					qcom,gpu-freq = <0>;

					qcom,bus-freq = <0>;

					qcom,bus-min = <0>;

					qcom,bus-max = <0>;

				};

			};



			qcom,gpu-pwrlevels-1 {

				#address-cells = <1>;

				#size-cells = <0>;



			compatible = "qcom,gpu-pwrlevels";

				qcom,speed-bin = <205>;



				qcom,initial-pwrlevel = <6>;

				qcom,ca-target-pwrlevel = <5>;



				/* TURBO_L1 */

				qcom,gpu-pwrlevel@0 {
@@ -235,6 +335,90 @@ 
					qcom,bus-max = <0>;

				};

			};



			qcom,gpu-pwrlevels-2 {

				#address-cells = <1>;

				#size-cells = <0>;



				qcom,speed-bin = <198>;



				qcom,initial-pwrlevel = <6>;

				qcom,ca-target-pwrlevel = <5>;



				/* TURBO_L1 */

				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <950000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <10>;

					qcom,bus-max = <11>;

				};



				/* TURBO */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <900000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <9>;

					qcom,bus-max = <11>;

				};



				/* NOM_L1 */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <820000000>;

					qcom,bus-freq = <10>;

					qcom,bus-min = <9>;

					qcom,bus-max = <11>;

				};



				/* NOM */

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <745000000>;

					qcom,bus-freq = <9>;

					qcom,bus-min = <8>;

					qcom,bus-max = <10>;

				};



				/* SVS_L1 */

				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <600000000>;

					qcom,bus-freq = <8>;

					qcom,bus-min = <7>;

					qcom,bus-max = <9>;

				};



				/* SVS */

				qcom,gpu-pwrlevel@5 {

					reg = <5>;

					qcom,gpu-freq = <465000000>;

					qcom,bus-freq = <7>;

					qcom,bus-min = <5>;

					qcom,bus-max = <8>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@6 {

					reg = <6>;

					qcom,gpu-freq = <320000000>;

					qcom,bus-freq = <4>;

					qcom,bus-min = <3>;

					qcom,bus-max = <5>;

				};



				/* XO */

				qcom,gpu-pwrlevel@7 {

					reg = <7>;

					qcom,gpu-freq = <0>;

					qcom,bus-freq = <0>;

					qcom,bus-min = <0>;

					qcom,bus-max = <0>;

				};

			};



		};

	};



	kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {