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Commit 272f3dab authored Apr 25, 2018 by Isaac J. Manjarres

ARM: dts: msm: Add support for L2 Cache dumping



Enable dumping of L2 cache on the sm8150's gold cluster.

Change-Id: I8e5892951ac45ef287a3d86f0e778d133dd3e9b4
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>

parent bf3742df

arch/arm64/boot/dts/qcom/sm8150.dtsi

+24 −0

Original line number	Diff line number	Diff line
		@@ -210,6 +210,7 @@
		cache-size = <0x40000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		qcom,dump-size = <0x88000>;
		};

		L1_I_400: l1-icache {
		@@ -251,6 +252,7 @@
		cache-size = <0x40000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		qcom,dump-size = <0x88000>;
		};

		L1_I_500: l1-icache {
		@@ -292,6 +294,7 @@
		cache-size = <0x40000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		qcom,dump-size = <0x88000>;
		};

		L1_I_600: l1-icache {
		@@ -333,6 +336,7 @@
		cache-size = <0x80000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		qcom,dump-size = <0x110000>;
		};

		L1_I_700: l1-icache {
		@@ -1952,6 +1956,26 @@
		qcom,dump-id = <0x47>;
		};

		qcom,l2_cache_dump400 {
		qcom,dump-node = <&L2_4>;
		qcom,dump-id = <0xc4>;
		};

		qcom,l2_cache_dump500 {
		qcom,dump-node = <&L2_5>;
		qcom,dump-id = <0xc5>;
		};

		qcom,l2_cache_dump600 {
		qcom,dump-node = <&L2_6>;
		qcom,dump-id = <0xc6>;
		};

		qcom,l2_cache_dump700 {
		qcom,dump-node = <&L2_7>;
		qcom,dump-id = <0xc7>;
		};

		qcom,l2_tlb_dump0 {
		qcom,dump-node = <&L2_TLB_0>;
		qcom,dump-id = <0x120>;