Merge "ARM: dts: Add clock measure support for DDR clock for SDXPRAIRIE" (271eb03e) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sdxprairie.dtsi

+9 −5

Original line number	Diff line number	Diff line
		@@ -326,9 +326,9 @@

		clock_debugcc: qcom,cc-debug {
		compatible = "qcom,debugcc-sdxprairie";
		qcom,cc-count = <2>;
		qcom,gcc = <&clock_gcc>;
		qcom,cpucc = <&cpucc_debug>;
		qcom,mccc = <&mccc_debug>;
		clock-names = "xo_clk_src";
		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		#clock-cells = <1>;
		@@ -336,9 +336,8 @@

		clock_cpu: qcom,clock-cpu@17808100 {
		compatible = "qcom,cpu-sdxprairie";
		clocks = <&clock_rpmh RPMH_CXO_CLK>,
		<&clock_gcc GPLL0>;
		clock-names = "bi_tcxo", "gpll0";
		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "bi_tcxo";
		reg = <0x17810008 0x8>,
		<0x17808100 0x44>;
		reg-names = "apcs_cmd" , "apcs_pll";
		@@ -349,7 +348,7 @@
		< 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
		< 576000000 RPMH_REGULATOR_LEVEL_SVS>,
		< 1094400000 RPMH_REGULATOR_LEVEL_NOM>,
		< 1497600000 RPMH_REGULATOR_LEVEL_TURBO>;
		< 1555200000 RPMH_REGULATOR_LEVEL_TURBO>;
		#clock-cells = <1>;
		};

		@@ -358,6 +357,11 @@
		reg = <0x1781101c 0x4>;
		};

		mccc_debug: syscon@90b0000 {
		compatible = "syscon";
		reg = <0x90b0000 0x800>;
		};

		spmi_bus: qcom,spmi@c440000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc440000 0xd00>,

drivers/clk/qcom/clk-alpha-pll.c

+14 −9

Original line number	Diff line number	Diff line
		@@ -158,7 +158,7 @@
		#define LUCID_PLL_STANDBY 0x0
		#define LUCID_PLL_RUN 0x1
		#define LUCID_PLL_OUT_MASK 0x7
		#define LUCID_PCAL_DONE BIT(26)
		#define LUCID_PCAL_DONE BIT(27)
		#define LUCID_PLL_RATE_MARGIN 500
		#define LUCID_PLL_ACK_LATCH BIT(29)
		#define LUCID_PLL_UPDATE BIT(22)
		@@ -2553,8 +2553,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw)
		return 0;

		/* Return early if calibration is not needed. */
		ret = regmap_read(pll->clkr.regmap, pll->offset + LUCID_PLL_OFF_STATUS,
		&regval);
		ret = regmap_read(pll->clkr.regmap, pll->offset, &regval);
		if (regval & LUCID_PCAL_DONE)
		return ret;

		@@ -2626,6 +2625,11 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
		if (ret)
		return ret;

		/*
		* When PLL_HW_UPDATE_LOGIC_BYPASS bit is not set then waiting for
		* pll_ack_latch to return to zero can be bypassed.
		*/
		if (!(pll->flags & SUPPORTS_NO_PLL_LATCH)) {
		/* Wait for 2 reference cycles before checking the ACK bit. */
		udelay(1);
		regmap_read(pll->clkr.regmap, pll->offset + PLL_MODE, &regval);
		@@ -2633,6 +2637,7 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
		WARN(1, "PLL latch failed. Output may be unstable!\n");
		return -EINVAL;
		}
		}

		/* Return the latch input to 0 */
		ret = regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE,

drivers/clk/qcom/clk-alpha-pll.h

+2 −1

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015, 2017-2019, The Linux Foundation. All rights reserved.
		*
		* This software is licensed under the terms of the GNU General Public
		* License version 2, as published by the Free Software Foundation, and
		@@ -77,6 +77,7 @@ struct clk_alpha_pll {
		/* Associated with soft_vote for multiple PLL software instances */
		#define SUPPORTS_FSM_VOTE BIT(5)
		#define SUPPORTS_NO_SLEW BIT(6)
		#define SUPPORTS_NO_PLL_LATCH BIT(7)
		u8 flags;

		struct clk_regmap clkr;

drivers/clk/qcom/clk-cpu-sdxprairie.c

+2 −42

Original line number	Diff line number	Diff line
		@@ -186,27 +186,6 @@ static u8 cpucc_clk_get_parent(struct clk_hw *hw)
		return clk_regmap_mux_div_ops.get_parent(hw);
		}

		/*
		* We use the notifier function for switching to a temporary safe configuration
		* (mux and divider), while the APSS pll is reconfigured.
		*/
		static int cpucc_notifier_cb(struct notifier_block *nb, unsigned long event,
		void *data)
		{
		struct clk_regmap_mux_div *cpuclk = container_of(nb,
		struct clk_regmap_mux_div, clk_nb);
		int ret = 0;

		if (event == PRE_RATE_CHANGE)
		/* set the mux to safe source(gpll0) & div */
		ret = __mux_div_set_src_div(cpuclk, cpuclk->safe_src, 1);

		if (event == ABORT_RATE_CHANGE)
		pr_err("Error in configuring PLL - stay at safe src only\n");

		return notifier_from_errno(ret);
		}

		static const struct clk_ops cpucc_clk_ops = {
		.enable = cpucc_clk_enable,
		.disable = cpucc_clk_disable,
		@@ -241,7 +220,7 @@ static struct clk_alpha_pll apcs_cpu_pll = {
		.type = LUCID_PLL,
		.vco_table = lucid_vco,
		.num_vco = ARRAY_SIZE(lucid_vco),
		.flags = SUPPORTS_NO_SLEW,
		.flags = SUPPORTS_NO_PLL_LATCH,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "apcs_cpu_pll",
		.parent_names = (const char *[]){ "bi_tcxo_ao" },
		@@ -263,10 +242,7 @@ static struct clk_regmap_mux_div apcs_mux_clk = {
		.hid_shift = 0,
		.src_width = 3,
		.src_shift = 8,
		.safe_src = 1,
		.safe_div = 1,
		.parent_map = apcs_mux_clk_parent_map,
		.clk_nb.notifier_call = cpucc_notifier_cb,
		.clkr.hw.init = &(struct clk_init_data) {
		.name = "apcs_mux_clk",
		.parent_names = apcs_mux_clk_parent_name,
		@@ -508,13 +484,6 @@ static int cpucc_driver_probe(struct platform_device *pdev)
		return PTR_ERR(clk);
		}

		clk = devm_clk_get(dev, "gpll0");
		if (IS_ERR(clk)) {
		if (PTR_ERR(clk) != -EPROBE_DEFER)
		dev_err(dev, "Unable to get GPLL0 clock\n");
		return PTR_ERR(clk);
		}

		/* Rail Regulator for apcs_cpu_pll & cpuss mux*/
		vdd_lucid_pll.regulator[0] = devm_regulator_get(&pdev->dev,
		"vdd-lucid-pll");
		@@ -613,13 +582,6 @@ static int cpucc_driver_probe(struct platform_device *pdev)
		return ret;
		}

		ret = clk_notifier_register(apcs_mux_clk.clkr.hw.clk,
		&apcs_mux_clk.clk_nb);
		if (ret) {
		dev_err(dev, "failed to register clock notifier: %d\n", ret);
		return ret;
		}

		/* Set to boot frequency */
		ret = clk_set_rate(apcs_mux_clk.clkr.hw.clk, cpucc_clk_init_rate);
		if (ret)
		@@ -750,8 +712,6 @@ static int __init cpu_clock_init(void)
		l_val = readl_relaxed(base + LUCID_PLL_OFF_L_VAL);
		}

		writel_relaxed(0xC05, base + LUCID_PLL_OFF_USER_CTL_U);

		cpucc_clk_init_rate = l_val * XO_RATE;

		regval = readl_relaxed(base);

drivers/clk/qcom/debugcc-sdxprairie.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -103,6 +103,7 @@ static struct clk_debug_mux gcc_debug_mux = {
		.src_sel_shift = 0,
		.post_div_mask = 0xF,
		.post_div_shift = 0,
		.period_offset = 0x50,
		MUX_SRC_LIST(
		{ "gcc_ahb_pcie_link_clk", 0xCF, 4, GCC,
		0xCF, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
		@@ -214,7 +215,7 @@ static struct clk_debug_mux gcc_debug_mux = {
		0x63, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
		{ "gcc_xo_pcie_link_clk", 0x77, 4, GCC,
		0x77, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
		{ "measure_only_bimc_clk", 0x73, 4, GCC,
		{ "measure_only_bimc_clk", 0x73, 4, MC_CC,
		0x73, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
		{ "measure_only_ipa_2x_clk", 0xAC, 4, GCC,
		0xAC, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
		@@ -280,6 +281,10 @@ static int clk_debug_sdxprairie_probe(struct platform_device *pdev)
		if (ret)
		return ret;

		ret = map_debug_bases(pdev, "qcom,mccc", MC_CC);
		if (ret)
		return ret;

		clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);
		if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Unable to register GCC debug mux\n");