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Commit 26f0ed3a authored by Mohammed Mirza Mandayappurath Manzoor's avatar Mohammed Mirza Mandayappurath Manzoor
Browse files

ARM: dts: msm: Expose NOM_L1 power level for supported devices 



Create speed bins to include NOM_L1 on supported A640 devices.
Add efuse memory region to identify supported devices.

Change-Id: I794aec37f80859c6f15be6658be20b9ecde56062
Signed-off-by: default avatarMohammed Mirza Mandayappurath Manzoor <mmandaya@codeaurora.org>
parent 4b042fdc

arch/arm64/boot/dts/qcom/sm8150-gpu-v2.dtsi

+6 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -14,6 +14,11 @@ 
	gpu_opp_table_v2: gpu_opp_table_v2 {

		compatible = "operating-points-v2";



		opp-675000000 {

			opp-hz = /bits/ 64 <675000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;

		};



		opp-585000000 {

			opp-hz = /bits/ 64 <585000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;

arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -68,8 +68,9 @@ 
		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		status = "ok";

		reg = <0x2c00000 0x40000>, <0x2c61000 0x800>,

				<0x6900000 0x44000>;

		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "qdss_gfx";

				<0x6900000 0x44000>, <0x780000 0x6fff>;

		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc",

					"qdss_gfx", "qfprom_memory";

		interrupts = <0 300 0>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+123 −51
Original line number Diff line number Diff line
@@ -588,7 +588,7 @@ 
	qcom,chipid = <0x06040001>;



	/* Power level to start throttling */

	qcom,throttle-pwrlevel = <3>;

	qcom,throttle-pwrlevel = <0>;



	/* Updated Bus Scale Settings */

	qcom,msm-bus,num-cases = <12>;
@@ -613,15 +613,24 @@ 
		<26 512 0 7211000>,    // 10 bus=1804

		<26 512 0 8363000>;    // 11 bus=2092



	qcom,initial-pwrlevel = <4>;

	/delete-property/qcom,initial-pwrlevel;



	operating-points-v2 = <&gpu_opp_table_v2>;



	qcom,gpu-pwrlevels {

	qcom,gpu-speed-bin = <0x4130 0xe0000000 29>;



	/delete-node/qcom,gpu-pwrlevels;

	qcom,gpu-pwrlevel-bins {

		#address-cells = <1>;

		#size-cells = <0>;



		compatible="qcom,gpu-pwrlevel-bins";

		qcom,gpu-pwrlevels-0 {

			#address-cells = <1>;

			#size-cells = <0>;



		compatible = "qcom,gpu-pwrlevels";

			qcom,speed-bin = <0>;

			qcom,initial-pwrlevel = <4>;



			qcom,gpu-pwrlevel@0 {

				reg = <0>;
@@ -670,7 +679,70 @@ 
				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		/delete-node/ qcom,gpu-pwrlevel@6;

		};

		qcom,gpu-pwrlevels-1 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <1>;

			qcom,initial-pwrlevel = <5>;



			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <675000000>;

				qcom,bus-freq = <11>;

				qcom,bus-min = <11>;

				qcom,bus-max = <11>;

			};



			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <585000000>;

				qcom,bus-freq = <10>;

				qcom,bus-min = <9>;

				qcom,bus-max = <11>;

			};



			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <499200000>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <11>;

			};



			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <427000000>;

				qcom,bus-freq = <6>;

				qcom,bus-min = <5>;

				qcom,bus-max = <9>;

			};



			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <345000000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <3>;

				qcom,bus-max = <5>;

			};



			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <257000000>;

				qcom,bus-freq = <3>;

				qcom,bus-min = <2>;

				qcom,bus-max = <4>;

			};



			qcom,gpu-pwrlevel@6 {

				reg = <6>;

				qcom,gpu-freq = <0>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};

	};



	qcom,l3-pwrlevels {