Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 26d6899b authored by Emil Tantilov's avatar Emil Tantilov Committed by Jeff Kirsher
Browse files

ixgbe: Fill out PCIe speed and width enums with values 



This patch fills in the values for bus speed and width of the
ixgbe_bus_speed and ixgbe_bus_width enums.

Signed-off-by: default avatarEmil Tantilov <emil.s.tantilov@intel.com>
Tested-by: default avatarStephen Ko <stephen.s.ko@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 1783575c

drivers/net/ixgbe/ixgbe_type.h

+11 −11
Original line number Diff line number Diff line
@@ -2333,25 +2333,25 @@ enum ixgbe_bus_type { 
/* PCI bus speeds */

enum ixgbe_bus_speed {

	ixgbe_bus_speed_unknown = 0,

	ixgbe_bus_speed_33,

	ixgbe_bus_speed_66,

	ixgbe_bus_speed_100,

	ixgbe_bus_speed_120,

	ixgbe_bus_speed_133,

	ixgbe_bus_speed_2500,

	ixgbe_bus_speed_5000,

	ixgbe_bus_speed_33      = 33,

	ixgbe_bus_speed_66      = 66,

	ixgbe_bus_speed_100     = 100,

	ixgbe_bus_speed_120     = 120,

	ixgbe_bus_speed_133     = 133,

	ixgbe_bus_speed_2500    = 2500,

	ixgbe_bus_speed_5000    = 5000,

	ixgbe_bus_speed_reserved

};



/* PCI bus widths */

enum ixgbe_bus_width {

	ixgbe_bus_width_unknown = 0,

	ixgbe_bus_width_pcie_x1,

	ixgbe_bus_width_pcie_x2,

	ixgbe_bus_width_pcie_x1 = 1,

	ixgbe_bus_width_pcie_x2 = 2,

	ixgbe_bus_width_pcie_x4 = 4,

	ixgbe_bus_width_pcie_x8 = 8,

	ixgbe_bus_width_32,

	ixgbe_bus_width_64,

	ixgbe_bus_width_32      = 32,

	ixgbe_bus_width_64      = 64,

	ixgbe_bus_width_reserved

};