Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 26ab96df authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Ralf Baechle
Browse files

MIPS: Add support for interAptiv cores 



The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit.

Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6163/
parent 0ce7d58e

arch/mips/include/asm/cpu-type.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ static inline int __pure __get_cpu_type(const int cpu_type) 
	case CPU_74K:

	case CPU_M14KC:

	case CPU_M14KEC:

	case CPU_INTERAPTIV:

	case CPU_PROAPTIV:

#endif

arch/mips/include/asm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -295,7 +295,7 @@ enum cpu_type_enum { 
	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,

	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,

	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,

	CPU_M14KEC, CPU_PROAPTIV,

	CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,



	/*

	 * MIPS64 class processors

arch/mips/kernel/idle.c

+1 −0
Original line number Diff line number Diff line
@@ -184,6 +184,7 @@ void __init check_wait(void) 
	case CPU_24K:

	case CPU_34K:

	case CPU_1004K:

	case CPU_INTERAPTIV:

	case CPU_PROAPTIV:

		cpu_wait = r4k_wait;

		if (read_c0_config7() & MIPS_CONF7_WII)

arch/mips/kernel/spram.c

+1 −0
Original line number Diff line number Diff line
@@ -206,6 +206,7 @@ void spram_config(void) 
	case CPU_34K:

	case CPU_74K:

	case CPU_1004K:

	case CPU_INTERAPTIV:

	case CPU_PROAPTIV:

		config0 = read_c0_config();

		/* FIXME: addresses are Malta specific */

arch/mips/kernel/traps.c

+1 −0
Original line number Diff line number Diff line
@@ -1337,6 +1337,7 @@ static inline void parity_protection_init(void) 
	case CPU_34K:

	case CPU_74K:

	case CPU_1004K:

	case CPU_INTERAPTIV:

	case CPU_PROAPTIV:

		{

#define ERRCTL_PE	0x80000000