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Commit 26a7e06d authored by Simon Horman's avatar Simon Horman
Browse files

arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support 



Initial version of Renesas R-Car H3 support (V10)

Signed-off-by: default avatarGaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: default avatarMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 8005c49d

Documentation/devicetree/bindings/arm/shmobile.txt

+2 −0
Original line number Original line Diff line number Diff line
@@ -27,6 +27,8 @@ SoCs: 
    compatible = "renesas,r8a7793"

    compatible = "renesas,r8a7793"

  - R-Car E2 (R8A77940)

  - R-Car E2 (R8A77940)

    compatible = "renesas,r8a7794"

    compatible = "renesas,r8a7794"

  - R-Car H3 (R8A77950)

    compatible = "renesas,r8a7795"









Boards:

Boards:

arch/arm64/Kconfig.platforms

+17 −0
Original line number Original line Diff line number Diff line
@@ -67,6 +67,23 @@ config ARCH_SEATTLE 
	help

	help

	  This enables support for AMD Seattle SOC Family

	  This enables support for AMD Seattle SOC Family





config ARCH_SHMOBILE

	bool



config ARCH_RENESAS

	bool "Renesas SoC Platforms"

	select ARCH_SHMOBILE

	select PINCTRL

	select PM_GENERIC_DOMAINS if PM

	help

	  This enables support for the ARMv8 based Renesas SoCs.



config ARCH_R8A7795

	bool "Renesas R-Car H3 SoC Platform"

	depends on ARCH_RENESAS

	help

	  This enables support for the Renesas R-Car H3 SoC.



config ARCH_STRATIX10

config ARCH_STRATIX10

	bool "Altera's Stratix 10 SoCFPGA Family"

	bool "Altera's Stratix 10 SoCFPGA Family"

	help

	help

arch/arm64/boot/dts/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -10,6 +10,7 @@ dts-dirs += hisilicon 
dts-dirs += marvell

dts-dirs += marvell

dts-dirs += mediatek

dts-dirs += mediatek

dts-dirs += qcom

dts-dirs += qcom

dts-dirs += renesas

dts-dirs += rockchip

dts-dirs += rockchip

dts-dirs += sprd

dts-dirs += sprd

dts-dirs += xilinx

dts-dirs += xilinx

arch/arm64/boot/dts/renesas/Makefile

0 → 100644
+2 −0
Original line number Original line Diff line number Diff line 
always		:= $(dtb-y)

clean-files	:= *.dtb

arch/arm64/boot/dts/renesas/r8a7795.dtsi

0 → 100644
+83 −0
Original line number Original line Diff line number Diff line 
/*

 * Device Tree Source for the r8a7795 SoC

 *

 * Copyright (C) 2015 Renesas Electronics Corp.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	compatible = "renesas,r8a7795";

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		/* 1 core only at this point */

		a57_0: cpu@0 {

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0x0>;

			device_type = "cpu";

		};

	};



	extal_clk: extal {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	extalr_clk: extalr {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	soc {

		compatible = "simple-bus";

		interrupt-parent = <&gic>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		gic: interrupt-controller@0xf1010000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

			reg = <0x0 0xf1010000 0 0x1000>,

			      <0x0 0xf1020000 0 0x2000>;

			interrupts = <GIC_PPI 9

					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;

		};



		timer {

			compatible = "arm,armv8-timer";

			interrupts = <GIC_PPI 13

					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 14

					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 11

					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 10

					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;

		};



		cpg: clock-controller@e6150000 {

			compatible = "renesas,r8a7795-cpg-mssr";

			reg = <0 0xe6150000 0 0x1000>;

			clocks = <&extal_clk>, <&extalr_clk>;

			clock-names = "extal", "extalr";

			#clock-cells = <2>;

			#power-domain-cells = <0>;

		};

	};

};