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Commit 2563afa9 authored by Florian Tobias Schandinat's avatar Florian Tobias Schandinat
Browse files

Merge branch 'viafb-pll' into viafb-next

parents bf5ea02d e4fcaeff

drivers/video/via/dvi.c

+3 −1
Original line number Diff line number Diff line
@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp, 
	struct crt_mode_table *pDviTiming;

	unsigned long desirePixelClock, maxPixelClock;

	pDviTiming = mode->crtc;

	desirePixelClock = pDviTiming->clk / 1000000;

	desirePixelClock = pDviTiming->refresh_rate

		* pDviTiming->crtc.hor_total * pDviTiming->crtc.ver_total

		/ 1000000;

	maxPixelClock = (unsigned long)viaparinfo->

		tmds_setting_info->max_pixel_clock;

drivers/video/via/hw.c

+350 −390
Original line number Diff line number Diff line
@@ -22,342 +22,272 @@ 
#include <linux/via-core.h>

#include "global.h"



static struct pll_map pll_value[] = {

	{25175000,

		{99, 7, 3},

		{85, 3, 4},	/* ignoring bit difference: 0x00008000 */

		{141, 5, 4},

		{141, 5, 4} },

	{29581000,

		{33, 4, 2},

		{66, 2, 4},	/* ignoring bit difference: 0x00808000 */

		{166, 5, 4},	/* ignoring bit difference: 0x00008000 */

		{165, 5, 4} },

	{26880000,

static struct pll_config cle266_pll_config[] = {

	{19, 4, 0},

	{26, 5, 0},

	{28, 5, 0},

	{31, 5, 0},

	{33, 5, 0},

	{55, 5, 0},

	{102, 5, 0},

	{53, 6, 0},

	{92, 6, 0},

	{98, 6, 0},

	{112, 6, 0},

	{41, 7, 0},

	{60, 7, 0},

	{99, 7, 0},

	{100, 7, 0},

	{83, 8, 0},

	{86, 8, 0},

	{108, 8, 0},

	{87, 9, 0},

	{118, 9, 0},

	{95, 12, 0},

	{115, 12, 0},

	{108, 13, 0},

	{83, 17, 0},

	{67, 20, 0},

	{86, 20, 0},

	{98, 20, 0},

	{121, 24, 0},

	{99, 29, 0},

	{33, 3, 1},

	{15, 4, 1},

		{30, 2, 3},	/* ignoring bit difference: 0x00808000 */

		{150, 5, 4},

		{150, 5, 4} },

	{31500000,

		{53, 3, 3},	/* ignoring bit difference: 0x00008000 */

		{141, 4, 4},	/* ignoring bit difference: 0x00008000 */

		{176, 5, 4},

		{176, 5, 4} },

	{31728000,

	{23, 4, 1},

	{37, 5, 1},

	{83, 5, 1},

	{85, 5, 1},

	{94, 5, 1},

	{103, 5, 1},

	{109, 5, 1},

	{113, 5, 1},

	{121, 5, 1},

	{82, 6, 1},

	{31, 7, 1},

		{177, 5, 4},	/* ignoring bit difference: 0x00008000 */

		{177, 5, 4},

		{142, 4, 4} },

	{32688000,

	{55, 7, 1},

	{84, 7, 1},

	{83, 8, 1},

	{76, 9, 1},

	{127, 9, 1},

	{33, 4, 2},

	{75, 4, 2},

	{119, 4, 2},

	{121, 4, 2},

	{91, 5, 2},

	{118, 5, 2},

	{83, 6, 2},

	{109, 6, 2},

	{90, 7, 2},

	{93, 2, 3},

	{53, 3, 3},

	{73, 4, 3},

		{146, 4, 4},	/* ignoring bit difference: 0x00008000 */

		{183, 5, 4},

		{146, 4, 4} },

	{36000000,

		{101, 5, 3},	/* ignoring bit difference: 0x00008000 */

		{161, 4, 4},	/* ignoring bit difference: 0x00008000 */

		{202, 5, 4},

		{161, 4, 4} },

	{40000000,

	{89, 4, 3},

		{89, 4, 3},	/* ignoring bit difference: 0x00008000 */

		{112, 5, 3},

		{112, 5, 3} },

	{41291000,

		{23, 4, 1},

		{69, 3, 3},	/* ignoring bit difference: 0x00008000 */

		{115, 5, 3},

		{115, 5, 3} },

	{43163000,

		{121, 5, 3},

		{121, 5, 3},	/* ignoring bit difference: 0x00008000 */

	{105, 4, 3},

	{117, 4, 3},

	{101, 5, 3},

	{121, 5, 3},

		{121, 5, 3} },

	{45250000,

	{127, 5, 3},

		{127, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{99, 7, 3}

};



static struct pll_config k800_pll_config[] = {

	{22, 2, 0},

	{28, 3, 0},

	{81, 3, 1},

	{85, 3, 1},

	{98, 3, 1},

	{112, 3, 1},

	{86, 4, 1},

	{166, 4, 1},

	{109, 5, 1},

	{113, 5, 1},

	{121, 5, 1},

	{131, 5, 1},

	{143, 5, 1},

	{153, 5, 1},

	{66, 3, 2},

	{68, 3, 2},

	{95, 3, 2},

	{106, 3, 2},

	{116, 3, 2},

	{93, 4, 2},

	{119, 4, 2},

	{121, 4, 2},

	{133, 4, 2},

	{137, 4, 2},

	{117, 5, 2},

	{118, 5, 2},

	{120, 5, 2},

	{124, 5, 2},

	{132, 5, 2},

	{137, 5, 2},

	{141, 5, 2},

	{166, 5, 2},

	{170, 5, 2},

	{191, 5, 2},

	{206, 5, 2},

	{208, 5, 2},

	{30, 2, 3},

	{69, 3, 3},

	{82, 3, 3},

	{83, 3, 3},

	{109, 3, 3},

	{114, 3, 3},

	{125, 3, 3},

	{89, 4, 3},

	{103, 4, 3},

	{117, 4, 3},

	{126, 4, 3},

	{150, 4, 3},

	{161, 4, 3},

	{121, 5, 3},

	{127, 5, 3},

		{127, 5, 3} },

	{46000000,

		{90, 7, 2},

		{103, 4, 3},	/* ignoring bit difference: 0x00008000 */

		{129, 5, 3},

		{103, 4, 3} },

	{46996000,

		{105, 4, 3},	/* ignoring bit difference: 0x00008000 */

		{131, 5, 3},	/* ignoring bit difference: 0x00808000 */

		{131, 5, 3},	/* ignoring bit difference: 0x00808000 */

		{105, 4, 3} },

	{48000000,

		{67, 20, 0},

		{134, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{131, 5, 3},

	{134, 5, 3},

		{134, 5, 3} },

	{48875000,

		{99, 29, 0},

		{82, 3, 3},	/* ignoring bit difference: 0x00808000 */

		{82, 3, 3},	/* ignoring bit difference: 0x00808000 */

		{137, 5, 3} },

	{49500000,

		{83, 6, 2},

		{83, 3, 3},	/* ignoring bit difference: 0x00008000 */

		{138, 5, 3},

		{83, 3, 3} },

	{52406000,

		{117, 4, 3},

		{117, 4, 3},	/* ignoring bit difference: 0x00008000 */

		{117, 4, 3},

		{88, 3, 3} },

	{52977000,

		{37, 5, 1},

		{148, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{148, 5, 3},

		{148, 5, 3} },

	{56250000,

		{55, 7, 1},	/* ignoring bit difference: 0x00008000 */

		{126, 4, 3},	/* ignoring bit difference: 0x00008000 */

		{157, 5, 3},

		{157, 5, 3} },

	{57275000,

		{0, 0, 0},

		{2, 2, 0},

		{2, 2, 0},

		{157, 5, 3} },	/* ignoring bit difference: 0x00808000 */

	{60466000,

		{76, 9, 1},

		{169, 5, 3},	/* ignoring bit difference: 0x00808000 */

		{169, 5, 3},	/* FIXED: old = {72, 2, 3} */

		{169, 5, 3} },

	{61500000,

		{86, 20, 0},

		{172, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{169, 5, 3},

	{172, 5, 3},

		{172, 5, 3} },

	{65000000,

		{109, 6, 2},	/* ignoring bit difference: 0x00008000 */

		{109, 3, 3},	/* ignoring bit difference: 0x00008000 */

		{109, 3, 3},

		{109, 3, 3} },

	{65178000,

		{91, 5, 2},

		{182, 5, 3},	/* ignoring bit difference: 0x00808000 */

		{109, 3, 3},

		{182, 5, 3} },

	{66750000,

		{75, 4, 2},

		{150, 4, 3},	/* ignoring bit difference: 0x00808000 */

		{150, 4, 3},

		{112, 3, 3} },

	{68179000,

		{19, 4, 0},

		{114, 3, 3},	/* ignoring bit difference: 0x00008000 */

		{190, 5, 3},

		{191, 5, 3} },

	{69924000,

		{83, 17, 0},

		{195, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{182, 5, 3},

	{195, 5, 3},

		{195, 5, 3} },

	{70159000,

		{98, 20, 0},

		{196, 5, 3},	/* ignoring bit difference: 0x00808000 */

	{196, 5, 3},

		{195, 5, 3} },

	{72000000,

		{121, 24, 0},

		{161, 4, 3},	/* ignoring bit difference: 0x00808000 */

		{161, 4, 3},

		{161, 4, 3} },

	{78750000,

		{33, 3, 1},

		{66, 3, 2},	/* ignoring bit difference: 0x00008000 */

	{208, 5, 3},

	{66, 2, 4},

	{85, 3, 4},

	{141, 4, 4},

	{146, 4, 4},

	{161, 4, 4},

	{177, 5, 4}

};



static struct pll_config cx700_pll_config[] = {

	{98, 3, 1},

	{86, 4, 1},

	{109, 5, 1},

	{110, 5, 1},

	{113, 5, 1},

	{121, 5, 1},

	{131, 5, 1},

	{135, 5, 1},

	{142, 5, 1},

	{143, 5, 1},

	{153, 5, 1},

	{187, 5, 1},

	{208, 5, 1},

	{68, 2, 2},

	{95, 3, 2},

	{116, 3, 2},

	{93, 4, 2},

	{119, 4, 2},

	{133, 4, 2},

	{137, 4, 2},

	{151, 4, 2},

	{166, 4, 2},

	{110, 5, 2},

		{110, 5, 2} },

	{80136000,

		{28, 5, 0},

		{68, 3, 2},	/* ignoring bit difference: 0x00008000 */

	{112, 5, 2},

		{112, 5, 2} },

	{83375000,

		{93, 2, 3},

		{93, 4, 2},	/* ignoring bit difference: 0x00800000 */

		{93, 4, 2},	/* ignoring bit difference: 0x00800000 */

		{117, 5, 2} },

	{83950000,

		{41, 7, 0},

		{117, 5, 2},	/* ignoring bit difference: 0x00008000 */

	{117, 5, 2},

		{117, 5, 2} },

	{84750000,

		{118, 5, 2},

		{118, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{118, 5, 2},

		{118, 5, 2} },

	{85860000,

		{84, 7, 1},

		{120, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{120, 5, 2},

		{118, 5, 2} },

	{88750000,

		{31, 5, 0},

		{124, 5, 2},	/* ignoring bit difference: 0x00808000 */

		{174, 7, 2},	/* ignoring bit difference: 0x00808000 */

		{124, 5, 2} },

	{94500000,

		{33, 5, 0},

		{132, 5, 2},	/* ignoring bit difference: 0x00008000 */

	{132, 5, 2},

		{132, 5, 2} },

	{97750000,

		{82, 6, 1},

		{137, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{137, 5, 2},

		{137, 5, 2} },

	{101000000,

		{127, 9, 1},

		{141, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{141, 5, 2},

		{141, 5, 2} },

	{106500000,

		{119, 4, 2},

		{119, 4, 2},	/* ignoring bit difference: 0x00808000 */

		{119, 4, 2},

		{149, 5, 2} },

	{108000000,

		{121, 4, 2},

		{121, 4, 2},	/* ignoring bit difference: 0x00808000 */

	{151, 5, 2},

		{151, 5, 2} },

	{113309000,

		{95, 12, 0},

		{95, 3, 2},	/* ignoring bit difference: 0x00808000 */

		{95, 3, 2},

		{159, 5, 2} },

	{118840000,

		{83, 5, 1},

		{166, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{166, 5, 2},

		{166, 5, 2} },

	{119000000,

		{108, 13, 0},

		{133, 4, 2},	/* ignoring bit difference: 0x00808000 */

		{133, 4, 2},

		{167, 5, 2} },

	{121750000,

		{85, 5, 1},

		{170, 5, 2},	/* ignoring bit difference: 0x00808000 */

		{68, 2, 2},

		{0, 0, 0} },

	{125104000,

		{53, 6, 0},	/* ignoring bit difference: 0x00008000 */

		{106, 3, 2},	/* ignoring bit difference: 0x00008000 */

	{175, 5, 2},

		{0, 0, 0} },

	{135000000,

		{94, 5, 1},

		{28, 3, 0},	/* ignoring bit difference: 0x00804000 */

		{151, 4, 2},

		{189, 5, 2} },

	{136700000,

		{115, 12, 0},

		{191, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{191, 5, 2},

		{191, 5, 2} },

	{138400000,

		{87, 9, 0},

		{116, 3, 2},	/* ignoring bit difference: 0x00808000 */

		{116, 3, 2},

		{194, 5, 2} },

	{146760000,

		{103, 5, 1},

		{206, 5, 2},	/* ignoring bit difference: 0x00808000 */

	{206, 5, 2},

		{206, 5, 2} },

	{153920000,

		{86, 8, 0},

		{86, 4, 1},	/* ignoring bit difference: 0x00808000 */

	{174, 7, 2},

	{82, 3, 3},

	{109, 3, 3},

	{117, 4, 3},

	{150, 4, 3},

	{161, 4, 3},

	{112, 5, 3},

	{115, 5, 3},

	{121, 5, 3},

	{127, 5, 3},

	{129, 5, 3},

	{131, 5, 3},

	{134, 5, 3},

	{138, 5, 3},

	{148, 5, 3},

	{157, 5, 3},

	{169, 5, 3},

	{172, 5, 3},

	{190, 5, 3},

	{195, 5, 3},

	{196, 5, 3},

	{208, 5, 3},

	{141, 5, 4},

	{150, 5, 4},

	{166, 5, 4},

	{176, 5, 4},

	{177, 5, 4},

	{183, 5, 4},

	{202, 5, 4}

};



static struct pll_config vx855_pll_config[] = {

	{86, 4, 1},

		{86, 4, 1} },	/* FIXED: old = {84, 2, 1} */

	{156000000,

		{109, 5, 1},

		{109, 5, 1},	/* ignoring bit difference: 0x00808000 */

		{109, 5, 1},

		{108, 5, 1} },

	{157500000,

		{55, 5, 0},	/* ignoring bit difference: 0x00008000 */

		{22, 2, 0},	/* ignoring bit difference: 0x00802000 */

	{108, 5, 1},

	{110, 5, 1},

		{110, 5, 1} },

	{162000000,

		{113, 5, 1},

		{113, 5, 1},	/* ignoring bit difference: 0x00808000 */

	{113, 5, 1},

		{113, 5, 1} },

	{187000000,

		{118, 9, 0},

		{131, 5, 1},	/* ignoring bit difference: 0x00808000 */

	{121, 5, 1},

	{131, 5, 1},

		{131, 5, 1} },

	{193295000,

		{108, 8, 0},

		{81, 3, 1},	/* ignoring bit difference: 0x00808000 */

	{135, 5, 1},

		{135, 5, 1} },

	{202500000,

		{99, 7, 0},

		{85, 3, 1},	/* ignoring bit difference: 0x00808000 */

	{142, 5, 1},

		{142, 5, 1} },

	{204000000,

		{100, 7, 0},

		{143, 5, 1},	/* ignoring bit difference: 0x00808000 */

	{143, 5, 1},

		{143, 5, 1} },

	{218500000,

		{92, 6, 0},

		{153, 5, 1},	/* ignoring bit difference: 0x00808000 */

	{153, 5, 1},

		{153, 5, 1} },

	{234000000,

		{98, 6, 0},

		{98, 3, 1},	/* ignoring bit difference: 0x00008000 */

		{98, 3, 1},

		{164, 5, 1} },

	{267250000,

		{112, 6, 0},

		{112, 3, 1},	/* ignoring bit difference: 0x00808000 */

	{164, 5, 1},

	{187, 5, 1},

		{187, 5, 1} },

	{297500000,

		{102, 5, 0},	/* ignoring bit difference: 0x00008000 */

		{166, 4, 1},	/* ignoring bit difference: 0x00008000 */

	{208, 5, 1},

		{208, 5, 1} },

	{74481000,

		{26, 5, 0},

		{125, 3, 3},	/* ignoring bit difference: 0x00808000 */

		{208, 5, 3},

		{209, 5, 3} },

	{172798000,

		{121, 5, 1},

		{121, 5, 1},	/* ignoring bit difference: 0x00808000 */

		{121, 5, 1},

		{121, 5, 1} },

	{122614000,

		{60, 7, 0},

		{137, 4, 2},	/* ignoring bit difference: 0x00808000 */

		{137, 4, 2},

		{172, 5, 2} },

	{74270000,

		{83, 8, 1},

		{208, 5, 3},

		{208, 5, 3},

		{0, 0, 0} },

	{148500000,

		{83, 8, 0},

	{110, 5, 2},

	{112, 5, 2},

	{117, 5, 2},

	{118, 5, 2},

	{124, 5, 2},

	{132, 5, 2},

	{137, 5, 2},

	{141, 5, 2},

	{149, 5, 2},

	{151, 5, 2},

	{159, 5, 2},

	{166, 5, 2},

	{167, 5, 2},

	{172, 5, 2},

	{189, 5, 2},

	{191, 5, 2},

	{194, 5, 2},

	{206, 5, 2},

	{208, 5, 2},

		{166, 4, 2},

		{208, 5, 2} }

	{83, 3, 3},

	{88, 3, 3},

	{109, 3, 3},

	{112, 3, 3},

	{103, 4, 3},

	{105, 4, 3},

	{161, 4, 3},

	{112, 5, 3},

	{115, 5, 3},

	{121, 5, 3},

	{127, 5, 3},

	{134, 5, 3},

	{137, 5, 3},

	{148, 5, 3},

	{157, 5, 3},

	{169, 5, 3},

	{172, 5, 3},

	{182, 5, 3},

	{191, 5, 3},

	{195, 5, 3},

	{209, 5, 3},

	{142, 4, 4},

	{146, 4, 4},

	{161, 4, 4},

	{141, 5, 4},

	{150, 5, 4},

	{165, 5, 4},

	{176, 5, 4}

};



/* according to VIA Technologies these values are based on experiment */
@@ -1692,44 +1622,64 @@ static u32 vx855_encode_pll(struct pll_config pll) 
		| pll.multiplier;

}



static inline u32 get_pll_internal_frequency(u32 ref_freq,

	struct pll_config pll)

{

	return ref_freq / pll.divisor * pll.multiplier;

}



static inline u32 get_pll_output_frequency(u32 ref_freq, struct pll_config pll)

{

	return get_pll_internal_frequency(ref_freq, pll)>>pll.rshift;

}



static struct pll_config get_pll_config(struct pll_config *config, int size,

	int clk)

{

	struct pll_config best = config[0];

	const u32 f0 = 14318180; /* X1 frequency */

	int i;



	for (i = 1; i < size; i++) {

		if (abs(get_pll_output_frequency(f0, config[i]) - clk)

			< abs(get_pll_output_frequency(f0, best) - clk))

			best = config[i];

	}



	return best;

}



u32 viafb_get_clk_value(int clk)

{

	u32 value = 0;

	int i = 0;



	while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)

		i++;



	if (i == NUM_TOTAL_PLL_TABLE) {

		printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");

	} else {

	switch (viaparinfo->chip_info->gfx_chip_name) {

	case UNICHROME_CLE266:

	case UNICHROME_K400:

			value = cle266_encode_pll(pll_value[i].cle266_pll);

		value = cle266_encode_pll(get_pll_config(cle266_pll_config,

			ARRAY_SIZE(cle266_pll_config), clk));

		break;



	case UNICHROME_K800:

	case UNICHROME_PM800:

	case UNICHROME_CN700:

			value = k800_encode_pll(pll_value[i].k800_pll);

		value = k800_encode_pll(get_pll_config(k800_pll_config,

			ARRAY_SIZE(k800_pll_config), clk));

		break;



	case UNICHROME_CX700:

	case UNICHROME_CN750:

	case UNICHROME_K8M890:

	case UNICHROME_P4M890:

	case UNICHROME_P4M900:

	case UNICHROME_VX800:

			value = k800_encode_pll(pll_value[i].cx700_pll);

		value = k800_encode_pll(get_pll_config(cx700_pll_config,

			ARRAY_SIZE(cx700_pll_config), clk));

		break;



	case UNICHROME_VX855:

	case UNICHROME_VX900:

			value = vx855_encode_pll(pll_value[i].vx855_pll);

		value = vx855_encode_pll(get_pll_config(vx855_pll_config,

			ARRAY_SIZE(vx855_pll_config), clk));

		break;

	}

	}



	return value;

}
@@ -2052,7 +2002,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 
	int i;

	int index = 0;

	int h_addr, v_addr;

	u32 pll_D_N;

	u32 pll_D_N, clock;



	for (i = 0; i < video_mode->mode_array; i++) {

		index = i;
@@ -2105,7 +2055,9 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 
	    && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))

		viafb_load_FIFO_reg(set_iga, h_addr, v_addr);



	pll_D_N = viafb_get_clk_value(crt_table[index].clk);

	clock = crt_reg.hor_total * crt_reg.ver_total

		* crt_table[index].refresh_rate;

	pll_D_N = viafb_get_clk_value(clock);

	DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);

	viafb_set_vclock(pll_D_N, set_iga);
@@ -2616,35 +2568,43 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, 
int viafb_get_pixclock(int hres, int vres, int vmode_refresh)

{

	int i;

	struct crt_mode_table *best;

	struct VideoModeTable *vmode = viafb_get_mode(hres, vres);



	for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {

		if ((hres == res_map_refresh_tbl[i].hres)

		    && (vres == res_map_refresh_tbl[i].vres)

		    && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))

			return res_map_refresh_tbl[i].pixclock;

	}

	if (!vmode)

		return RES_640X480_60HZ_PIXCLOCK;



	best = &vmode->crtc[0];

	for (i = 1; i < vmode->mode_array; i++) {

		if (abs(vmode->crtc[i].refresh_rate - vmode_refresh)

			< abs(best->refresh_rate - vmode_refresh))

			best = &vmode->crtc[i];

	}



	return 1000000000 / (best->crtc.hor_total * best->crtc.ver_total)

		* 1000 / best->refresh_rate;

}



int viafb_get_refresh(int hres, int vres, u32 long_refresh)

{

#define REFRESH_TOLERANCE 3

	int i, nearest = -1, diff = REFRESH_TOLERANCE;

	for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {

		if ((hres == res_map_refresh_tbl[i].hres)

		    && (vres == res_map_refresh_tbl[i].vres)

		    && (diff > (abs(long_refresh -

		    res_map_refresh_tbl[i].vmode_refresh)))) {

			diff = abs(long_refresh - res_map_refresh_tbl[i].

				vmode_refresh);

			nearest = i;

		}

	}

#undef REFRESH_TOLERANCE

	if (nearest > 0)

		return res_map_refresh_tbl[nearest].vmode_refresh;

	int i;

	struct crt_mode_table *best;

	struct VideoModeTable *vmode = viafb_get_mode(hres, vres);



	if (!vmode)

		return 60;



	best = &vmode->crtc[0];

	for (i = 1; i < vmode->mode_array; i++) {

		if (abs(vmode->crtc[i].refresh_rate - long_refresh)

			< abs(best->refresh_rate - long_refresh))

			best = &vmode->crtc[i];

	}



	if (abs(best->refresh_rate - long_refresh) > 3)

		return 60;



	return best->refresh_rate;

}



static void device_off(void)

drivers/video/via/hw.h

+0 −2
Original line number Diff line number Diff line
@@ -893,8 +893,6 @@ struct iga2_crtc_timing { 
/* VT3410 chipset*/

#define VX900_FUNCTION3     0x3410



#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)



struct IODATA {

	u8 Index;

	u8 Mask;

drivers/video/via/lcd.c

+5 −3
Original line number Diff line number Diff line
@@ -562,7 +562,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, 
	int set_vres = plvds_setting_info->v_active;

	int panel_hres = plvds_setting_info->lcd_panel_hres;

	int panel_vres = plvds_setting_info->lcd_panel_vres;

	u32 pll_D_N;

	u32 pll_D_N, clock;

	struct display_timing mode_crt_reg, panel_crt_reg;

	struct crt_mode_table *panel_crt_table = NULL;

	struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
@@ -577,7 +577,9 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, 
	DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");

	if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)

		viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);

	plvds_setting_info->vclk = panel_crt_table->clk;

	clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total

		* panel_crt_table->refresh_rate;

	plvds_setting_info->vclk = clock;

	if (set_iga == IGA1) {

		/* IGA1 doesn't have LCD scaling, so set it as centering. */

		viafb_load_crtc_timing(lcd_centering_timging
@@ -612,7 +614,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, 


	fill_lcd_format();



	pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);

	pll_D_N = viafb_get_clk_value(clock);

	DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);

	viafb_set_vclock(pll_D_N, set_iga);

	lcd_patch_skew(plvds_setting_info, plvds_chip_info);

drivers/video/via/share.h

+0 −141
Original line number Diff line number Diff line
@@ -627,77 +627,6 @@ 
#define M2048x1536_R60_HSP      NEGATIVE

#define M2048x1536_R60_VSP      POSITIVE



/* define PLL index: */

#define CLK_25_175M     25175000

#define CLK_26_880M     26880000

#define CLK_29_581M     29581000

#define CLK_31_500M     31500000

#define CLK_31_728M     31728000

#define CLK_32_668M     32688000

#define CLK_36_000M     36000000

#define CLK_40_000M     40000000

#define CLK_41_291M     41291000

#define CLK_43_163M     43163000

#define CLK_45_250M     45250000	/* 45.46MHz */

#define CLK_46_000M     46000000

#define CLK_46_996M     46996000

#define CLK_48_000M     48000000

#define CLK_48_875M     48875000

#define CLK_49_500M     49500000

#define CLK_52_406M     52406000

#define CLK_52_977M     52977000

#define CLK_56_250M     56250000

#define CLK_57_275M     57275000

#define CLK_60_466M     60466000

#define CLK_61_500M     61500000

#define CLK_65_000M     65000000

#define CLK_65_178M     65178000

#define CLK_66_750M     66750000	/* 67.116MHz */

#define CLK_68_179M     68179000

#define CLK_69_924M     69924000

#define CLK_70_159M     70159000

#define CLK_72_000M     72000000

#define CLK_74_270M     74270000

#define CLK_78_750M     78750000

#define CLK_80_136M     80136000

#define CLK_83_375M     83375000

#define CLK_83_950M     83950000

#define CLK_84_750M     84750000	/* 84.537Mhz */

#define CLK_85_860M     85860000

#define CLK_88_750M     88750000

#define CLK_94_500M     94500000

#define CLK_97_750M     97750000

#define CLK_101_000M    101000000

#define CLK_106_500M    106500000

#define CLK_108_000M    108000000

#define CLK_113_309M    113309000

#define CLK_118_840M    118840000

#define CLK_119_000M    119000000

#define CLK_121_750M    121750000	/* 121.704MHz */

#define CLK_125_104M    125104000

#define CLK_135_000M    135000000

#define CLK_136_700M    136700000

#define CLK_138_400M    138400000

#define CLK_146_760M    146760000

#define CLK_148_500M    148500000



#define CLK_153_920M    153920000

#define CLK_156_000M    156000000

#define CLK_157_500M    157500000

#define CLK_162_000M    162000000

#define CLK_187_000M    187000000

#define CLK_193_295M    193295000

#define CLK_202_500M    202500000

#define CLK_204_000M    204000000

#define CLK_218_500M    218500000

#define CLK_234_000M    234000000

#define CLK_267_250M    267250000

#define CLK_297_500M    297500000

#define CLK_74_481M     74481000

#define CLK_172_798M    172798000

#define CLK_122_614M    122614000





/* Definition CRTC Timing Index */

#define H_TOTAL_INDEX               0

#define H_ADDR_INDEX                1
@@ -722,76 +651,7 @@ 


/* Definition Video Mode Pixel Clock (picoseconds)

*/

#define RES_480X640_60HZ_PIXCLOCK    39722

#define RES_640X480_60HZ_PIXCLOCK    39722

#define RES_640X480_75HZ_PIXCLOCK    31747

#define RES_640X480_85HZ_PIXCLOCK    27777

#define RES_640X480_100HZ_PIXCLOCK   23168

#define RES_640X480_120HZ_PIXCLOCK   19081

#define RES_720X480_60HZ_PIXCLOCK    37020

#define RES_720X576_60HZ_PIXCLOCK    30611

#define RES_800X600_60HZ_PIXCLOCK    25000

#define RES_800X600_75HZ_PIXCLOCK    20203

#define RES_800X600_85HZ_PIXCLOCK    17777

#define RES_800X600_100HZ_PIXCLOCK   14667

#define RES_800X600_120HZ_PIXCLOCK   11912

#define RES_800X480_60HZ_PIXCLOCK    33805

#define RES_848X480_60HZ_PIXCLOCK    31756

#define RES_856X480_60HZ_PIXCLOCK    31518

#define RES_1024X512_60HZ_PIXCLOCK   24218

#define RES_1024X600_60HZ_PIXCLOCK   20460

#define RES_1024X768_60HZ_PIXCLOCK   15385

#define RES_1024X768_75HZ_PIXCLOCK   12699

#define RES_1024X768_85HZ_PIXCLOCK   10582

#define RES_1024X768_100HZ_PIXCLOCK  8825

#define RES_1152X864_75HZ_PIXCLOCK   9259

#define RES_1280X768_60HZ_PIXCLOCK   12480

#define RES_1280X800_60HZ_PIXCLOCK   11994

#define RES_1280X960_60HZ_PIXCLOCK   9259

#define RES_1280X1024_60HZ_PIXCLOCK  9260

#define RES_1280X1024_75HZ_PIXCLOCK  7408

#define RES_1280X768_85HZ_PIXCLOCK   6349

#define RES_1440X1050_60HZ_PIXCLOCK  7993

#define RES_1600X1200_60HZ_PIXCLOCK  6172

#define RES_1600X1200_75HZ_PIXCLOCK  4938

#define RES_1280X720_60HZ_PIXCLOCK   13426

#define RES_1200X900_60HZ_PIXCLOCK   17459

#define RES_1920X1080_60HZ_PIXCLOCK  5787

#define RES_1400X1050_60HZ_PIXCLOCK  8214

#define RES_1400X1050_75HZ_PIXCLOCK  6410

#define RES_1368X768_60HZ_PIXCLOCK   11647

#define RES_960X600_60HZ_PIXCLOCK      22099

#define RES_1000X600_60HZ_PIXCLOCK    20834

#define RES_1024X576_60HZ_PIXCLOCK    21278

#define RES_1088X612_60HZ_PIXCLOCK    18877

#define RES_1152X720_60HZ_PIXCLOCK    14981

#define RES_1200X720_60HZ_PIXCLOCK    14253

#define RES_1280X600_60HZ_PIXCLOCK    16260

#define RES_1280X720_50HZ_PIXCLOCK    16538

#define RES_1280X768_50HZ_PIXCLOCK    15342

#define RES_1366X768_50HZ_PIXCLOCK    14301

#define RES_1366X768_60HZ_PIXCLOCK    11646

#define RES_1360X768_60HZ_PIXCLOCK    11799

#define RES_1440X900_60HZ_PIXCLOCK    9390

#define RES_1440X900_75HZ_PIXCLOCK    7315

#define RES_1600X900_60HZ_PIXCLOCK    8415

#define RES_1600X1024_60HZ_PIXCLOCK   7315

#define RES_1680X1050_60HZ_PIXCLOCK   6814

#define RES_1680X1050_75HZ_PIXCLOCK   5348

#define RES_1792X1344_60HZ_PIXCLOCK   4902

#define RES_1856X1392_60HZ_PIXCLOCK   4577

#define RES_1920X1200_60HZ_PIXCLOCK   5173

#define RES_1920X1440_60HZ_PIXCLOCK   4274

#define RES_1920X1440_75HZ_PIXCLOCK   3367

#define RES_2048X1536_60HZ_PIXCLOCK   3742



#define RES_1360X768_RB_60HZ_PIXCLOCK 13889

#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901

#define RES_1440X900_RB_60HZ_PIXCLOCK   11268

#define RES_1600X900_RB_60HZ_PIXCLOCK   10230

#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403

#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225

#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497



/* LCD display method

*/
@@ -822,7 +682,6 @@ struct display_timing { 


struct crt_mode_table {

	int refresh_rate;

	unsigned long clk;

	int h_sync_polarity;

	int v_sync_polarity;

	struct display_timing crtc;