Loading arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi +5 −4 Original line number Diff line number Diff line Loading @@ -447,8 +447,8 @@ &dsi_sw43404_amoled_fhd_plus_cmd { qcom,ulps-enabled; qcom,mdss-dsi-t-clk-post = <0x0A>; qcom,mdss-dsi-t-clk-pre = <0x21>; qcom,mdss-dsi-t-clk-post = <0x09>; qcom,mdss-dsi-t-clk-pre = <0x1B>; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; Loading @@ -458,8 +458,9 @@ qcom,mdss-dsi-panel-status-read-length = <1>; qcom,mdss-dsi-display-timings { timing@0{ qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05 05 03 02 04 00]; qcom,mdss-dsi-panel-phy-timings = [00 0F 03 03 1E 1D 04 04 02 03 04 00]; qcom,mdss-dsi-panel-clockrate = <354585600>; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; Loading drivers/gpu/drm/msm/dp/dp_catalog.c +6 −6 Original line number Diff line number Diff line Loading @@ -59,17 +59,17 @@ } static u8 const vm_pre_emphasis[4][4] = { {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */ {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */ {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */ {0x00, 0x0B, 0x14, 0xFF}, /* pe0, 0 db */ {0x00, 0x0B, 0x12, 0xFF}, /* pe1, 3.5 db */ {0x00, 0x0B, 0xFF, 0xFF}, /* pe2, 6.0 db */ {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */ }; /* voltage swing, 0.2v and 1.0v are not support */ static u8 const vm_voltage_swing[4][4] = { {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */ {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */ {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */ {0x07, 0x0F, 0x16, 0xFF}, /* sw0, 0.4v */ {0x11, 0x1E, 0x1F, 0xFF}, /* sw1, 0.6 v */ {0x19, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */ {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */ }; Loading drivers/gpu/drm/msm/dp/dp_catalog_v200.c +73 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,24 @@ dp_catalog->priv.data; \ }) #define MAX_VOLTAGE_LEVELS 4 #define MAX_PRE_EMP_LEVELS 4 static u8 const vm_pre_emphasis[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = { {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */ {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */ {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */ {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */ }; /* voltage swing, 0.2v and 1.0v are not support */ static u8 const vm_voltage_swing[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = { {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */ {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */ {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */ {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */ }; struct dp_catalog_io { struct dp_io_data *dp_ahb; struct dp_io_data *dp_aux; Loading Loading @@ -185,6 +203,60 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel, dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_NVID, nvid); } static void dp_catalog_ctrl_update_vx_px_v200(struct dp_catalog_ctrl *ctrl, u8 v_level, u8 p_level) { struct dp_catalog_private_v200 *catalog; struct dp_io_data *io_data; u8 value0, value1; if (!ctrl || !((v_level < MAX_VOLTAGE_LEVELS) && (p_level < MAX_PRE_EMP_LEVELS))) { pr_err("invalid input\n"); return; } catalog = dp_catalog_get_priv_v200(ctrl); pr_debug("hw: v=%d p=%d\n", v_level, p_level); value0 = vm_voltage_swing[v_level][p_level]; value1 = vm_pre_emphasis[v_level][p_level]; /* program default setting first */ io_data = catalog->io->dp_ln_tx0; dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, 0x2A); dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20); io_data = catalog->io->dp_ln_tx1; dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, 0x2A); dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20); /* Enable MUX to use Cursor values from these registers */ value0 |= BIT(5); value1 |= BIT(5); /* Configure host and panel only if both values are allowed */ if (value0 != 0xFF && value1 != 0xFF) { io_data = catalog->io->dp_ln_tx0; dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, value0); dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, value1); io_data = catalog->io->dp_ln_tx1; dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, value0); dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, value1); pr_debug("hw: vx_value=0x%x px_value=0x%x\n", value0, value1); } else { pr_err("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n", v_level, value0, p_level, value1); } } static void dp_catalog_ctrl_lane_mapping_v200(struct dp_catalog_ctrl *ctrl, bool flipped, char *lane_map) { Loading Loading @@ -290,6 +362,7 @@ int dp_catalog_get_v200(struct device *dev, struct dp_catalog *catalog, catalog->panel.config_msa = dp_catalog_panel_config_msa_v200; catalog->ctrl.update_vx_px = dp_catalog_ctrl_update_vx_px_v200; catalog->ctrl.lane_mapping = dp_catalog_ctrl_lane_mapping_v200; catalog->ctrl.usb_reset = dp_catalog_ctrl_usb_reset_v200; Loading drivers/gpu/drm/msm/dp/dp_mst_drm.c +9 −1 Original line number Diff line number Diff line Loading @@ -139,6 +139,13 @@ struct dp_mst_encoder_info_cache { struct dp_mst_private dp_mst; struct dp_mst_encoder_info_cache dp_mst_enc_cache; static void dp_mst_sim_destroy_port(struct kref *ref) { struct drm_dp_mst_port *port = container_of(ref, struct drm_dp_mst_port, kref); kfree(port); } /* DRM DP MST Framework simulator OPs */ static void dp_mst_sim_add_port(struct dp_mst_private *mst, struct dp_mst_sim_port_data *port_msg) Loading Loading @@ -183,13 +190,14 @@ static void dp_mst_sim_add_port(struct dp_mst_private *mst, mutex_lock(&mstb->mgr->lock); list_del(&port->next); mutex_unlock(&mstb->mgr->lock); kref_put(&port->kref, dp_mst_sim_destroy_port); goto put_port; } (*mstb->mgr->cbs->register_connector)(port->connector); } put_port: kref_put(&port->kref, NULL); kref_put(&port->kref, dp_mst_sim_destroy_port); } static void dp_mst_sim_link_probe_work(struct work_struct *work) Loading drivers/gpu/drm/msm/dp/dp_panel.c +7 −1 Original line number Diff line number Diff line Loading @@ -1646,13 +1646,16 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) panel->vscext_chaining_supported); skip_dpcd_read: link_info->revision = dpcd[DP_DPCD_REV]; panel->major = (link_info->revision >> 4) & 0x0f; panel->minor = link_info->revision & 0x0f; /* override link params updated in dp_panel_init_panel_info */ link_info->rate = min_t(unsigned long, panel->parser->max_lclk_khz, link_info->rate); drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE])); link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; if (multi_func) link_info->num_lanes = min_t(unsigned int, link_info->num_lanes, 2); Loading @@ -1660,6 +1663,9 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) pr_debug("version:%d.%d, rate:%d, lanes:%d\n", panel->major, panel->minor, link_info->rate, link_info->num_lanes); if (drm_dp_enhanced_frame_cap(dpcd)) link_info->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; dfp_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_DOWN_STREAM_PORT_COUNT; Loading Loading
arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi +5 −4 Original line number Diff line number Diff line Loading @@ -447,8 +447,8 @@ &dsi_sw43404_amoled_fhd_plus_cmd { qcom,ulps-enabled; qcom,mdss-dsi-t-clk-post = <0x0A>; qcom,mdss-dsi-t-clk-pre = <0x21>; qcom,mdss-dsi-t-clk-post = <0x09>; qcom,mdss-dsi-t-clk-pre = <0x1B>; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; Loading @@ -458,8 +458,9 @@ qcom,mdss-dsi-panel-status-read-length = <1>; qcom,mdss-dsi-display-timings { timing@0{ qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05 05 03 02 04 00]; qcom,mdss-dsi-panel-phy-timings = [00 0F 03 03 1E 1D 04 04 02 03 04 00]; qcom,mdss-dsi-panel-clockrate = <354585600>; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; Loading
drivers/gpu/drm/msm/dp/dp_catalog.c +6 −6 Original line number Diff line number Diff line Loading @@ -59,17 +59,17 @@ } static u8 const vm_pre_emphasis[4][4] = { {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */ {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */ {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */ {0x00, 0x0B, 0x14, 0xFF}, /* pe0, 0 db */ {0x00, 0x0B, 0x12, 0xFF}, /* pe1, 3.5 db */ {0x00, 0x0B, 0xFF, 0xFF}, /* pe2, 6.0 db */ {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */ }; /* voltage swing, 0.2v and 1.0v are not support */ static u8 const vm_voltage_swing[4][4] = { {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */ {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */ {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */ {0x07, 0x0F, 0x16, 0xFF}, /* sw0, 0.4v */ {0x11, 0x1E, 0x1F, 0xFF}, /* sw1, 0.6 v */ {0x19, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */ {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */ }; Loading
drivers/gpu/drm/msm/dp/dp_catalog_v200.c +73 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,24 @@ dp_catalog->priv.data; \ }) #define MAX_VOLTAGE_LEVELS 4 #define MAX_PRE_EMP_LEVELS 4 static u8 const vm_pre_emphasis[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = { {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */ {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */ {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */ {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */ }; /* voltage swing, 0.2v and 1.0v are not support */ static u8 const vm_voltage_swing[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = { {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */ {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */ {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */ {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */ }; struct dp_catalog_io { struct dp_io_data *dp_ahb; struct dp_io_data *dp_aux; Loading Loading @@ -185,6 +203,60 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel, dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_NVID, nvid); } static void dp_catalog_ctrl_update_vx_px_v200(struct dp_catalog_ctrl *ctrl, u8 v_level, u8 p_level) { struct dp_catalog_private_v200 *catalog; struct dp_io_data *io_data; u8 value0, value1; if (!ctrl || !((v_level < MAX_VOLTAGE_LEVELS) && (p_level < MAX_PRE_EMP_LEVELS))) { pr_err("invalid input\n"); return; } catalog = dp_catalog_get_priv_v200(ctrl); pr_debug("hw: v=%d p=%d\n", v_level, p_level); value0 = vm_voltage_swing[v_level][p_level]; value1 = vm_pre_emphasis[v_level][p_level]; /* program default setting first */ io_data = catalog->io->dp_ln_tx0; dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, 0x2A); dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20); io_data = catalog->io->dp_ln_tx1; dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, 0x2A); dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20); /* Enable MUX to use Cursor values from these registers */ value0 |= BIT(5); value1 |= BIT(5); /* Configure host and panel only if both values are allowed */ if (value0 != 0xFF && value1 != 0xFF) { io_data = catalog->io->dp_ln_tx0; dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, value0); dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, value1); io_data = catalog->io->dp_ln_tx1; dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, value0); dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, value1); pr_debug("hw: vx_value=0x%x px_value=0x%x\n", value0, value1); } else { pr_err("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n", v_level, value0, p_level, value1); } } static void dp_catalog_ctrl_lane_mapping_v200(struct dp_catalog_ctrl *ctrl, bool flipped, char *lane_map) { Loading Loading @@ -290,6 +362,7 @@ int dp_catalog_get_v200(struct device *dev, struct dp_catalog *catalog, catalog->panel.config_msa = dp_catalog_panel_config_msa_v200; catalog->ctrl.update_vx_px = dp_catalog_ctrl_update_vx_px_v200; catalog->ctrl.lane_mapping = dp_catalog_ctrl_lane_mapping_v200; catalog->ctrl.usb_reset = dp_catalog_ctrl_usb_reset_v200; Loading
drivers/gpu/drm/msm/dp/dp_mst_drm.c +9 −1 Original line number Diff line number Diff line Loading @@ -139,6 +139,13 @@ struct dp_mst_encoder_info_cache { struct dp_mst_private dp_mst; struct dp_mst_encoder_info_cache dp_mst_enc_cache; static void dp_mst_sim_destroy_port(struct kref *ref) { struct drm_dp_mst_port *port = container_of(ref, struct drm_dp_mst_port, kref); kfree(port); } /* DRM DP MST Framework simulator OPs */ static void dp_mst_sim_add_port(struct dp_mst_private *mst, struct dp_mst_sim_port_data *port_msg) Loading Loading @@ -183,13 +190,14 @@ static void dp_mst_sim_add_port(struct dp_mst_private *mst, mutex_lock(&mstb->mgr->lock); list_del(&port->next); mutex_unlock(&mstb->mgr->lock); kref_put(&port->kref, dp_mst_sim_destroy_port); goto put_port; } (*mstb->mgr->cbs->register_connector)(port->connector); } put_port: kref_put(&port->kref, NULL); kref_put(&port->kref, dp_mst_sim_destroy_port); } static void dp_mst_sim_link_probe_work(struct work_struct *work) Loading
drivers/gpu/drm/msm/dp/dp_panel.c +7 −1 Original line number Diff line number Diff line Loading @@ -1646,13 +1646,16 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) panel->vscext_chaining_supported); skip_dpcd_read: link_info->revision = dpcd[DP_DPCD_REV]; panel->major = (link_info->revision >> 4) & 0x0f; panel->minor = link_info->revision & 0x0f; /* override link params updated in dp_panel_init_panel_info */ link_info->rate = min_t(unsigned long, panel->parser->max_lclk_khz, link_info->rate); drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE])); link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; if (multi_func) link_info->num_lanes = min_t(unsigned int, link_info->num_lanes, 2); Loading @@ -1660,6 +1663,9 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) pr_debug("version:%d.%d, rate:%d, lanes:%d\n", panel->major, panel->minor, link_info->rate, link_info->num_lanes); if (drm_dp_enhanced_frame_cap(dpcd)) link_info->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; dfp_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_DOWN_STREAM_PORT_COUNT; Loading