Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 249516c9 authored by Lee Jones's avatar Lee Jones Committed by Brian Norris
Browse files

mtd: st_spi_fsm: Update the flash Volatile Configuration Register



The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare the message sequence responsible for updating a chip's VCR.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
parent 0de08e43
Loading
Loading
Loading
Loading
+32 −0
Original line number Original line Diff line number Diff line
@@ -415,6 +415,23 @@ static struct stfsm_seq stfsm_seq_erase_sector = {
		    SEQ_CFG_STARTSEQ),
		    SEQ_CFG_STARTSEQ),
};
};


static struct stfsm_seq stfsm_seq_wrvcr = {
	.seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
		       SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT),
	.seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
		       SEQ_OPC_OPCODE(FLASH_CMD_WRVCR)),
	.seq = {
		STFSM_INST_CMD1,
		STFSM_INST_CMD2,
		STFSM_INST_STA_WR1,
		STFSM_INST_STOP,
	},
	.seq_cfg = (SEQ_CFG_PADS_1 |
		    SEQ_CFG_READNOTWRITE |
		    SEQ_CFG_CSDEASSERT |
		    SEQ_CFG_STARTSEQ),
};

static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)
static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)
{
{
	seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
	seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
@@ -542,6 +559,21 @@ static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)
	return 0;
	return 0;
}
}


static int stfsm_wrvcr(struct stfsm *fsm, uint8_t data)
{
	struct stfsm_seq *seq = &stfsm_seq_wrvcr;

	dev_dbg(fsm->dev, "writing VCR 0x%02x\n", data);

	seq->status = (STA_DATA_BYTE1(data) | STA_PADS_1 | STA_CSDEASSERT);

	stfsm_load_seq(fsm, seq);

	stfsm_wait_seq(fsm);

	return 0;
}

/*
/*
 * SoC reset on 'boot-from-spi' systems
 * SoC reset on 'boot-from-spi' systems
 *
 *