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Commit 232ea344 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf: Fix loss of notification with multi-event
  perf, x86: Force IBS LVT offset assignment for family 10h
  perf, x86: Disable PEBS on SandyBridge chips
  trace_events_filter: Use rcu_assign_pointer() when setting ftrace_event_call->filter
  perf session: Fix crash with invalid CPU list
  perf python: Fix undefined symbol problem
  perf/x86: Enable raw event access to Intel offcore events
  perf: Don't use -ENOSPC for out of PMU resources
  perf: Do not set task_ctx pointer in cpuctx if there are no events in the context
  perf/x86: Fix PEBS instruction unwind
  oprofile, x86: Fix crash when unloading module (nmi timer mode)
  oprofile: Fix crash when unloading module (hr timer mode)
parents 40c043b0 dc440d10

arch/arm/kernel/perf_event.c

+3 −3
Original line number Diff line number Diff line
@@ -353,15 +353,15 @@ validate_group(struct perf_event *event) 
	fake_pmu.used_mask = fake_used_mask;



	if (!validate_event(&fake_pmu, leader))

		return -ENOSPC;

		return -EINVAL;



	list_for_each_entry(sibling, &leader->sibling_list, group_entry) {

		if (!validate_event(&fake_pmu, sibling))

			return -ENOSPC;

			return -EINVAL;

	}



	if (!validate_event(&fake_pmu, event))

		return -ENOSPC;

		return -EINVAL;



	return 0;

}

arch/mips/kernel/perf_event_mipsxx.c

+4 −4
Original line number Diff line number Diff line
@@ -623,7 +623,7 @@ static int mipspmu_event_init(struct perf_event *event) 
	if (!atomic_inc_not_zero(&active_events)) {

		if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {

			atomic_dec(&active_events);

			return -ENOSPC;

			return -EINVAL;

		}



		mutex_lock(&pmu_reserve_mutex);
@@ -732,15 +732,15 @@ static int validate_group(struct perf_event *event) 
	memset(&fake_cpuc, 0, sizeof(fake_cpuc));



	if (!validate_event(&fake_cpuc, leader))

		return -ENOSPC;

		return -EINVAL;



	list_for_each_entry(sibling, &leader->sibling_list, group_entry) {

		if (!validate_event(&fake_cpuc, sibling))

			return -ENOSPC;

			return -EINVAL;

	}



	if (!validate_event(&fake_cpuc, event))

		return -ENOSPC;

		return -EINVAL;



	return 0;

}

arch/x86/kernel/cpu/perf_event.c

+6 −10
Original line number Diff line number Diff line
@@ -312,12 +312,8 @@ int x86_setup_perfctr(struct perf_event *event) 
			return -EOPNOTSUPP;

	}



	/*

	 * Do not allow config1 (extended registers) to propagate,

	 * there's no sane user-space generalization yet:

	 */

	if (attr->type == PERF_TYPE_RAW)

		return 0;

		return x86_pmu_extra_regs(event->attr.config, event);



	if (attr->type == PERF_TYPE_HW_CACHE)

		return set_ext_hw_attr(hwc, event);
@@ -588,7 +584,7 @@ int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) 
				x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);

		}

	}

	return num ? -ENOSPC : 0;

	return num ? -EINVAL : 0;

}



/*
@@ -607,7 +603,7 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, 


	if (is_x86_event(leader)) {

		if (n >= max_count)

			return -ENOSPC;

			return -EINVAL;

		cpuc->event_list[n] = leader;

		n++;

	}
@@ -620,7 +616,7 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, 
			continue;



		if (n >= max_count)

			return -ENOSPC;

			return -EINVAL;



		cpuc->event_list[n] = event;

		n++;
@@ -1316,7 +1312,7 @@ static int validate_event(struct perf_event *event) 
	c = x86_pmu.get_event_constraints(fake_cpuc, event);



	if (!c || !c->weight)

		ret = -ENOSPC;

		ret = -EINVAL;



	if (x86_pmu.put_event_constraints)

		x86_pmu.put_event_constraints(fake_cpuc, event);
@@ -1341,7 +1337,7 @@ static int validate_group(struct perf_event *event) 
{

	struct perf_event *leader = event->group_leader;

	struct cpu_hw_events *fake_cpuc;

	int ret = -ENOSPC, n;

	int ret = -EINVAL, n;



	fake_cpuc = allocate_fake_cpuc();

	if (IS_ERR(fake_cpuc))

arch/x86/kernel/cpu/perf_event_amd_ibs.c

+18 −11
Original line number Diff line number Diff line
@@ -199,8 +199,7 @@ static int force_ibs_eilvt_setup(void) 
		goto out;

	}



	pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset);

	pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");

	pr_info("IBS: LVT offset %d assigned\n", offset);



	return 0;

out:
@@ -265,19 +264,23 @@ perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *h 
static __init int amd_ibs_init(void)

{

	u32 caps;

	int ret;

	int ret = -EINVAL;



	caps = __get_ibs_caps();

	if (!caps)

		return -ENODEV;	/* ibs not supported by the cpu */



	if (!ibs_eilvt_valid()) {

		ret = force_ibs_eilvt_setup();

		if (ret) {

			pr_err("Failed to setup IBS, %d\n", ret);

			return ret;

		}

	}

	/*

	 * Force LVT offset assignment for family 10h: The offsets are

	 * not assigned by the BIOS for this family, so the OS is

	 * responsible for doing it. If the OS assignment fails, fall

	 * back to BIOS settings and try to setup this.

	 */

	if (boot_cpu_data.x86 == 0x10)

		force_ibs_eilvt_setup();



	if (!ibs_eilvt_valid())

		goto out;



	get_online_cpus();

	ibs_caps = caps;
@@ -287,7 +290,11 @@ static __init int amd_ibs_init(void) 
	smp_call_function(setup_APIC_ibs, NULL, 1);

	put_online_cpus();



	return perf_event_ibs_init();

	ret = perf_event_ibs_init();

out:

	if (ret)

		pr_err("Failed to setup IBS, %d\n", ret);

	return ret;

}



/* Since we need the pci subsystem to init ibs we can't do this earlier: */

arch/x86/kernel/cpu/perf_event_intel.c

+8 −0
Original line number Diff line number Diff line
@@ -1545,6 +1545,13 @@ static void intel_clovertown_quirks(void) 
	x86_pmu.pebs_constraints = NULL;

}



static void intel_sandybridge_quirks(void)

{

	printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");

	x86_pmu.pebs = 0;

	x86_pmu.pebs_constraints = NULL;

}



__init int intel_pmu_init(void)

{

	union cpuid10_edx edx;
@@ -1694,6 +1701,7 @@ __init int intel_pmu_init(void) 
		break;



	case 42: /* SandyBridge */

		x86_pmu.quirks = intel_sandybridge_quirks;

	case 45: /* SandyBridge, "Romely-EP" */

		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));