Loading arch/arm64/boot/dts/qcom/sm8150-sde.dtsi +6 −4 Original line number Diff line number Diff line Loading @@ -26,11 +26,13 @@ <&clock_gcc GCC_DISP_HF_AXI_CLK>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>; clock-names = "gcc_iface", "gcc_bus", "iface_clk", "core_clk", "vsync_clk"; clock-rate = <0 0 0 300000000 19200000>; clock-max-rate = <0 0 0 460000000 19200000>; "iface_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0 0 0 300000000 19200000 300000000>; clock-max-rate = <0 0 0 460000000 19200000 460000000>; sde-vdd-supply = <&mdss_core_gdsc>; Loading Loading
arch/arm64/boot/dts/qcom/sm8150-sde.dtsi +6 −4 Original line number Diff line number Diff line Loading @@ -26,11 +26,13 @@ <&clock_gcc GCC_DISP_HF_AXI_CLK>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>; clock-names = "gcc_iface", "gcc_bus", "iface_clk", "core_clk", "vsync_clk"; clock-rate = <0 0 0 300000000 19200000>; clock-max-rate = <0 0 0 460000000 19200000>; "iface_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0 0 0 300000000 19200000 300000000>; clock-max-rate = <0 0 0 460000000 19200000 460000000>; sde-vdd-supply = <&mdss_core_gdsc>; Loading