Loading drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1.c +3 −3 Original line number Diff line number Diff line Loading @@ -435,7 +435,7 @@ static int validate_dma_cfg(struct sde_reg_dma_setup_ops_cfg *cfg) } if (cfg->dma_buf->iova & GUARD_BYTES || !cfg->dma_buf->vaddr) { DRM_ERROR("iova not aligned to %zx iova %x kva %pK", DRM_ERROR("iova not aligned to %zx iova %llx kva %pK", ADDR_ALIGN, cfg->dma_buf->iova, cfg->dma_buf->vaddr); return -EINVAL; Loading Loading @@ -494,8 +494,8 @@ static int validate_kick_off_v1(struct sde_reg_dma_kickoff_cfg *cfg) (WRITE_TRIGGER); if (cfg->dma_buf->iova & GUARD_BYTES) { DRM_ERROR("Address is not aligned to %zx iova %x", ADDR_ALIGN, cfg->dma_buf->iova); DRM_ERROR("Address is not aligned to %zx iova %llx", ADDR_ALIGN, cfg->dma_buf->iova); return -EINVAL; } Loading drivers/gpu/drm/msm/sde/sde_plane.c +1 −1 Original line number Diff line number Diff line Loading @@ -1810,7 +1810,7 @@ static int sde_plane_rot_calc_cfg(struct drm_plane *plane, if (attached_out_rect.y1 != rstate->out_src_rect.y1 || attached_out_rect.y2 != rstate->out_src_rect.y2) { SDE_ERROR( "plane%d.%u src:%dx%d+%d+%d rot:0x%llx fb:%d plane%d.%u src:%dx%d+%d+%d rot:0x%llx fb:%d mismatch\n", "plane%d.%u src:%dx%d+%d+%d rot:0x%x fb:%d plane%d.%u src:%dx%d+%d+%d rot:0x%x fb:%d mismatch\n", plane->base.id, rstate->sequence_id, state->src_w >> 16, Loading Loading
drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1.c +3 −3 Original line number Diff line number Diff line Loading @@ -435,7 +435,7 @@ static int validate_dma_cfg(struct sde_reg_dma_setup_ops_cfg *cfg) } if (cfg->dma_buf->iova & GUARD_BYTES || !cfg->dma_buf->vaddr) { DRM_ERROR("iova not aligned to %zx iova %x kva %pK", DRM_ERROR("iova not aligned to %zx iova %llx kva %pK", ADDR_ALIGN, cfg->dma_buf->iova, cfg->dma_buf->vaddr); return -EINVAL; Loading Loading @@ -494,8 +494,8 @@ static int validate_kick_off_v1(struct sde_reg_dma_kickoff_cfg *cfg) (WRITE_TRIGGER); if (cfg->dma_buf->iova & GUARD_BYTES) { DRM_ERROR("Address is not aligned to %zx iova %x", ADDR_ALIGN, cfg->dma_buf->iova); DRM_ERROR("Address is not aligned to %zx iova %llx", ADDR_ALIGN, cfg->dma_buf->iova); return -EINVAL; } Loading
drivers/gpu/drm/msm/sde/sde_plane.c +1 −1 Original line number Diff line number Diff line Loading @@ -1810,7 +1810,7 @@ static int sde_plane_rot_calc_cfg(struct drm_plane *plane, if (attached_out_rect.y1 != rstate->out_src_rect.y1 || attached_out_rect.y2 != rstate->out_src_rect.y2) { SDE_ERROR( "plane%d.%u src:%dx%d+%d+%d rot:0x%llx fb:%d plane%d.%u src:%dx%d+%d+%d rot:0x%llx fb:%d mismatch\n", "plane%d.%u src:%dx%d+%d+%d rot:0x%x fb:%d plane%d.%u src:%dx%d+%d+%d rot:0x%x fb:%d mismatch\n", plane->base.id, rstate->sequence_id, state->src_w >> 16, Loading