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Commit 229fd4a5 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

clk: qcom: Add support for banked MD RCGs 



The banked MD RCGs in global clock control have a different
register layout than the ones implemented in multimedia clock
control. Add support for these types of clocks so we can change
the rates of the UBI32 clocks.

Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent ae3669ac

drivers/clk/qcom/clk-rcg.c

+52 −47
Original line number Original line Diff line number Diff line
@@ -68,16 +68,16 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw) 
{

{

	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);

	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);

	int num_parents = __clk_get_num_parents(hw->clk);

	int num_parents = __clk_get_num_parents(hw->clk);

	u32 ns, ctl;

	u32 ns, reg;

	int bank;

	int bank;

	int i;

	int i;

	struct src_sel *s;

	struct src_sel *s;





	regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);

	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);

	bank = reg_to_bank(rcg, ctl);

	bank = reg_to_bank(rcg, reg);

	s = &rcg->s[bank];

	s = &rcg->s[bank];





	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);

	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);

	ns = ns_to_src(s, ns);

	ns = ns_to_src(s, ns);





	for (i = 0; i < num_parents; i++)

	for (i = 0; i < num_parents; i++)
@@ -193,90 +193,93 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val) 




static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)

static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)

{

{

	u32 ns, md, ctl, *regp;

	u32 ns, md, reg;

	int bank, new_bank;

	int bank, new_bank;

	struct mn *mn;

	struct mn *mn;

	struct pre_div *p;

	struct pre_div *p;

	struct src_sel *s;

	struct src_sel *s;

	bool enabled;

	bool enabled;

	u32 md_reg;

	u32 md_reg, ns_reg;

	u32 bank_reg;

	bool banked_mn = !!rcg->mn[1].width;

	bool banked_mn = !!rcg->mn[1].width;

	bool banked_p = !!rcg->p[1].pre_div_width;

	struct clk_hw *hw = &rcg->clkr.hw;

	struct clk_hw *hw = &rcg->clkr.hw;





	enabled = __clk_is_enabled(hw->clk);

	enabled = __clk_is_enabled(hw->clk);





	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);

	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);

	regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);

	bank = reg_to_bank(rcg, reg);



	if (banked_mn) {

		regp = &ctl;

		bank_reg = rcg->clkr.enable_reg;

	} else {

		regp = &ns;

		bank_reg = rcg->ns_reg;

	}



	bank = reg_to_bank(rcg, *regp);

	new_bank = enabled ? !bank : bank;

	new_bank = enabled ? !bank : bank;





	ns_reg = rcg->ns_reg[new_bank];

	regmap_read(rcg->clkr.regmap, ns_reg, &ns);



	if (banked_mn) {

	if (banked_mn) {

		mn = &rcg->mn[new_bank];

		mn = &rcg->mn[new_bank];

		md_reg = rcg->md_reg[new_bank];

		md_reg = rcg->md_reg[new_bank];





		ns |= BIT(mn->mnctr_reset_bit);

		ns |= BIT(mn->mnctr_reset_bit);

		regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);

		regmap_write(rcg->clkr.regmap, ns_reg, ns);





		regmap_read(rcg->clkr.regmap, md_reg, &md);

		regmap_read(rcg->clkr.regmap, md_reg, &md);

		md = mn_to_md(mn, f->m, f->n, md);

		md = mn_to_md(mn, f->m, f->n, md);

		regmap_write(rcg->clkr.regmap, md_reg, md);

		regmap_write(rcg->clkr.regmap, md_reg, md);





		ns = mn_to_ns(mn, f->m, f->n, ns);

		ns = mn_to_ns(mn, f->m, f->n, ns);

		regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);

		regmap_write(rcg->clkr.regmap, ns_reg, ns);





		ctl = mn_to_reg(mn, f->m, f->n, ctl);

		/* Two NS registers means mode control is in NS register */

		regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);

		if (rcg->ns_reg[0] != rcg->ns_reg[1]) {

			ns = mn_to_reg(mn, f->m, f->n, ns);

			regmap_write(rcg->clkr.regmap, ns_reg, ns);

		} else {

			reg = mn_to_reg(mn, f->m, f->n, reg);

			regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);

		}





		ns &= ~BIT(mn->mnctr_reset_bit);

		ns &= ~BIT(mn->mnctr_reset_bit);

		regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);

		regmap_write(rcg->clkr.regmap, ns_reg, ns);

	} else {

	}



	if (banked_p) {

		p = &rcg->p[new_bank];

		p = &rcg->p[new_bank];

		ns = pre_div_to_ns(p, f->pre_div - 1, ns);

		ns = pre_div_to_ns(p, f->pre_div - 1, ns);

	}

	}





	s = &rcg->s[new_bank];

	s = &rcg->s[new_bank];

	ns = src_to_ns(s, s->parent_map[f->src], ns);

	ns = src_to_ns(s, s->parent_map[f->src], ns);

	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);

	regmap_write(rcg->clkr.regmap, ns_reg, ns);





	if (enabled) {

	if (enabled) {

		*regp ^= BIT(rcg->mux_sel_bit);

		regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);

		regmap_write(rcg->clkr.regmap, bank_reg, *regp);

		reg ^= BIT(rcg->mux_sel_bit);

		regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);

	}

	}

}

}





static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)

static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)

{

{

	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);

	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);

	u32 ns, ctl, md, reg;

	u32 ns, md, reg;

	int bank;

	int bank;

	struct freq_tbl f = { 0 };

	struct freq_tbl f = { 0 };

	bool banked_mn = !!rcg->mn[1].width;

	bool banked_mn = !!rcg->mn[1].width;

	bool banked_p = !!rcg->p[1].pre_div_width;





	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);

	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);

	regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);

	reg = banked_mn ? ctl : ns;



	bank = reg_to_bank(rcg, reg);

	bank = reg_to_bank(rcg, reg);





	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);



	if (banked_mn) {

	if (banked_mn) {

		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);

		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);

		f.m = md_to_m(&rcg->mn[bank], md);

		f.m = md_to_m(&rcg->mn[bank], md);

		f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);

		f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);

	} else {

		f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;

	}

	}

	f.src = index;





	if (banked_p)

		f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;



	f.src = index;

	configure_bank(rcg, &f);

	configure_bank(rcg, &f);





	return 0;

	return 0;
@@ -337,28 +340,30 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	u32 m, n, pre_div, ns, md, mode, reg;

	u32 m, n, pre_div, ns, md, mode, reg;

	int bank;

	int bank;

	struct mn *mn;

	struct mn *mn;

	bool banked_p = !!rcg->p[1].pre_div_width;

	bool banked_mn = !!rcg->mn[1].width;

	bool banked_mn = !!rcg->mn[1].width;





	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);

	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);



	if (banked_mn)

		regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &reg);

	else

		reg = ns;



	bank = reg_to_bank(rcg, reg);

	bank = reg_to_bank(rcg, reg);





	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);

	m = n = pre_div = mode = 0;



	if (banked_mn) {

	if (banked_mn) {

		mn = &rcg->mn[bank];

		mn = &rcg->mn[bank];

		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);

		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);

		m = md_to_m(mn, md);

		m = md_to_m(mn, md);

		n = ns_m_to_n(mn, ns, m);

		n = ns_m_to_n(mn, ns, m);

		/* Two NS registers means mode control is in NS register */

		if (rcg->ns_reg[0] != rcg->ns_reg[1])

			reg = ns;

		mode = reg_to_mnctr_mode(mn, reg);

		mode = reg_to_mnctr_mode(mn, reg);

		return calc_rate(parent_rate, m, n, mode, 0);

	} else {

		pre_div = ns_to_pre_div(&rcg->p[bank], ns);

		return calc_rate(parent_rate, 0, 0, 0, pre_div);

	}

	}



	if (banked_p)

		pre_div = ns_to_pre_div(&rcg->p[bank], ns);



	return calc_rate(parent_rate, m, n, mode, pre_div);

}

}





static long _freq_tbl_determine_rate(struct clk_hw *hw,

static long _freq_tbl_determine_rate(struct clk_hw *hw,

drivers/clk/qcom/clk-rcg.h

+4 −2
Original line number Original line Diff line number Diff line
@@ -103,8 +103,9 @@ extern const struct clk_ops clk_rcg_bypass_ops; 
 * struct clk_dyn_rcg - root clock generator with glitch free mux

 * struct clk_dyn_rcg - root clock generator with glitch free mux

 *

 *

 * @mux_sel_bit: bit to switch glitch free mux

 * @mux_sel_bit: bit to switch glitch free mux

 * @ns_reg: NS register

 * @ns_reg: NS0 and NS1 register

 * @md_reg: MD0 and MD1 register

 * @md_reg: MD0 and MD1 register

 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux

 * @mn: mn counter (banked)

 * @mn: mn counter (banked)

 * @s: source selector (banked)

 * @s: source selector (banked)

 * @freq_tbl: frequency table

 * @freq_tbl: frequency table
@@ -113,8 +114,9 @@ extern const struct clk_ops clk_rcg_bypass_ops; 
 *

 *

 */

 */

struct clk_dyn_rcg {

struct clk_dyn_rcg {

	u32	ns_reg;

	u32	ns_reg[2];

	u32	md_reg[2];

	u32	md_reg[2];

	u32	bank_reg;





	u8	mux_sel_bit;

	u8	mux_sel_bit;

drivers/clk/qcom/mmcc-msm8960.c

+21 −7
Original line number Original line Diff line number Diff line
@@ -773,9 +773,11 @@ static struct freq_tbl clk_tbl_gfx2d[] = { 
};

};





static struct clk_dyn_rcg gfx2d0_src = {

static struct clk_dyn_rcg gfx2d0_src = {

	.ns_reg = 0x0070,

	.ns_reg[0] = 0x0070,

	.ns_reg[1] = 0x0070,

	.md_reg[0] = 0x0064,

	.md_reg[0] = 0x0064,

	.md_reg[1] = 0x0068,

	.md_reg[1] = 0x0068,

	.bank_reg = 0x0060,

	.mn[0] = {

	.mn[0] = {

		.mnctr_en_bit = 8,

		.mnctr_en_bit = 8,

		.mnctr_reset_bit = 25,

		.mnctr_reset_bit = 25,
@@ -831,9 +833,11 @@ static struct clk_branch gfx2d0_clk = { 
};

};





static struct clk_dyn_rcg gfx2d1_src = {

static struct clk_dyn_rcg gfx2d1_src = {

	.ns_reg = 0x007c,

	.ns_reg[0] = 0x007c,

	.ns_reg[1] = 0x007c,

	.md_reg[0] = 0x0078,

	.md_reg[0] = 0x0078,

	.md_reg[1] = 0x006c,

	.md_reg[1] = 0x006c,

	.bank_reg = 0x0074,

	.mn[0] = {

	.mn[0] = {

		.mnctr_en_bit = 8,

		.mnctr_en_bit = 8,

		.mnctr_reset_bit = 25,

		.mnctr_reset_bit = 25,
@@ -930,9 +934,11 @@ static struct freq_tbl clk_tbl_gfx3d_8064[] = { 
};

};





static struct clk_dyn_rcg gfx3d_src = {

static struct clk_dyn_rcg gfx3d_src = {

	.ns_reg = 0x008c,

	.ns_reg[0] = 0x008c,

	.ns_reg[1] = 0x008c,

	.md_reg[0] = 0x0084,

	.md_reg[0] = 0x0084,

	.md_reg[1] = 0x0088,

	.md_reg[1] = 0x0088,

	.bank_reg = 0x0080,

	.mn[0] = {

	.mn[0] = {

		.mnctr_en_bit = 8,

		.mnctr_en_bit = 8,

		.mnctr_reset_bit = 25,

		.mnctr_reset_bit = 25,
@@ -1006,9 +1012,11 @@ static struct freq_tbl clk_tbl_vcap[] = { 
};

};





static struct clk_dyn_rcg vcap_src = {

static struct clk_dyn_rcg vcap_src = {

	.ns_reg = 0x021c,

	.ns_reg[0] = 0x021c,

	.ns_reg[1] = 0x021c,

	.md_reg[0] = 0x01ec,

	.md_reg[0] = 0x01ec,

	.md_reg[1] = 0x0218,

	.md_reg[1] = 0x0218,

	.bank_reg = 0x0178,

	.mn[0] = {

	.mn[0] = {

		.mnctr_en_bit = 8,

		.mnctr_en_bit = 8,

		.mnctr_reset_bit = 23,

		.mnctr_reset_bit = 23,
@@ -1211,9 +1219,11 @@ static struct freq_tbl clk_tbl_mdp[] = { 
};

};





static struct clk_dyn_rcg mdp_src = {

static struct clk_dyn_rcg mdp_src = {

	.ns_reg = 0x00d0,

	.ns_reg[0] = 0x00d0,

	.ns_reg[1] = 0x00d0,

	.md_reg[0] = 0x00c4,

	.md_reg[0] = 0x00c4,

	.md_reg[1] = 0x00c8,

	.md_reg[1] = 0x00c8,

	.bank_reg = 0x00c0,

	.mn[0] = {

	.mn[0] = {

		.mnctr_en_bit = 8,

		.mnctr_en_bit = 8,

		.mnctr_reset_bit = 31,

		.mnctr_reset_bit = 31,
@@ -1318,7 +1328,9 @@ static struct freq_tbl clk_tbl_rot[] = { 
};

};





static struct clk_dyn_rcg rot_src = {

static struct clk_dyn_rcg rot_src = {

	.ns_reg = 0x00e8,

	.ns_reg[0] = 0x00e8,

	.ns_reg[1] = 0x00e8,

	.bank_reg = 0x00e8,

	.p[0] = {

	.p[0] = {

		.pre_div_shift = 22,

		.pre_div_shift = 22,

		.pre_div_width = 4,

		.pre_div_width = 4,
@@ -1542,9 +1554,11 @@ static struct freq_tbl clk_tbl_vcodec[] = { 
};

};





static struct clk_dyn_rcg vcodec_src = {

static struct clk_dyn_rcg vcodec_src = {

	.ns_reg = 0x0100,

	.ns_reg[0] = 0x0100,

	.ns_reg[1] = 0x0100,

	.md_reg[0] = 0x00fc,

	.md_reg[0] = 0x00fc,

	.md_reg[1] = 0x0128,

	.md_reg[1] = 0x0128,

	.bank_reg = 0x00f8,

	.mn[0] = {

	.mn[0] = {

		.mnctr_en_bit = 5,

		.mnctr_en_bit = 5,

		.mnctr_reset_bit = 31,

		.mnctr_reset_bit = 31,