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Commit 229ec356 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Enable CPU clock scaling for SDMMAGPIE"

parents d96627d1 5df073a0

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -874,8 +874,10 @@ 
			<0x18325800 0x1400>;

		reg-names = "osm_l3_base", "osm_pwrcl_base",

			"osm_perfcl_base";

		l3-devs = <&cpu0_cpu_l3_lat &cpu6_cpu_l3_lat

			   &cdsp_cdsp_l3_lat>;



		#clock-cells = <1>;

		status = "disabled";

	};



	cpucc_debug: syscon@182a0018 {

drivers/clk/qcom/camcc-sdmmagpie.c

+2 −2
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
#include "clk-regmap.h"

#include "common.h"

#include "reset.h"

#include "vdd-level.h"

#include "vdd-level-sdmmagpie.h"



#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -188,7 +188,7 @@ static const struct parent_map cam_cc_parent_map_9[] = { 
};



static const char * const cam_cc_parent_names_9[] = {

	"bi_tcxo",

	"bi_tcxo_ao",

	"core_bi_pll_test_se",

};

drivers/clk/qcom/dispcc-sdmmagpie.c

+7 −6
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
#include "clk-regmap-divider.h"

#include "common.h"

#include "reset.h"

#include "vdd-level.h"

#include "vdd-level-sdmmagpie.h"



#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -93,6 +93,11 @@ static const char * const disp_cc_parent_names_2[] = { 
	"core_bi_pll_test_se",

};



static const char * const disp_cc_parent_names_ao[] = {

	"bi_tcxo_ao",

	"core_bi_pll_test_se",

};



static const struct parent_map disp_cc_parent_map_3[] = {

	{ P_BI_TCXO, 0 },

	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
@@ -562,13 +567,9 @@ static struct clk_rcg2 disp_cc_xo_clk_src = { 
	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_xo_clk_src",

		.parent_names = disp_cc_parent_names_2,

		.parent_names = disp_cc_parent_names_ao,

		.num_parents = 2,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 19200000},

	},

};

drivers/clk/qcom/gcc-sdmmagpie.c

+5 −3
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
#include "clk-branch.h"

#include "clk-rcg.h"

#include "clk-regmap.h"

#include "vdd-level.h"

#include "vdd-level-sdmmagpie.h"



#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -1504,7 +1504,7 @@ static struct clk_branch gcc_disp_gpll0_div_clk_src = { 
		.hw.init = &(struct clk_init_data){

			.name = "gcc_disp_gpll0_div_clk_src",

			.parent_names = (const char *[]){

				"gcc_gpll0_main_div_cdiv",

				"gcc_pll0_main_div_cdiv",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,
@@ -1646,7 +1646,7 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 
		.hw.init = &(struct clk_init_data){

			.name = "gcc_gpu_gpll0_div_clk_src",

			.parent_names = (const char *[]){

				"gcc_gpll0_main_div_cdiv",

				"gcc_pll0_main_div_cdiv",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,
@@ -2674,6 +2674,7 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 
};



static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {

	.halt_reg = 0x7701c,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x7701c,
@@ -2686,6 +2687,7 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 
};



static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {

	.halt_reg = 0x77018,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x77018,

drivers/clk/qcom/gpucc-sdmmagpie.c

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
#include "clk-regmap.h"

#include "common.h"

#include "reset.h"

#include "vdd-level.h"

#include "vdd-level-sdmmagpie.h"



#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }