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Commit 21461775 authored by Tomasz Nowicki's avatar Tomasz Nowicki Committed by Bjorn Helgaas
Browse files

x86/PCI: Clarify AMD Fam10h config access restrictions comment 



Clarify the comment about AMD Fam10h config access restrictions, fix typos,
and add a reference to the specification.

[bhelgaas: streamline]
Signed-off-by: default avatarTomasz Nowicki <tomasz.nowicki@linaro.org>
Signed-off-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Tested-by: default avatarSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
parent 4066df63

arch/x86/include/asm/pci_x86.h

+5 −5
Original line number Diff line number Diff line
@@ -151,11 +151,11 @@ extern struct list_head pci_mmcfg_list; 
#define PCI_MMCFG_BUS_OFFSET(bus)      ((bus) << 20)



/*

 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space

 * on their northbrige except through the * %eax register. As such, you MUST

 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config

 * accessor functions.

 * In fact just use pci_config_*, nothing else please.

 * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use

 * %eax.  No other source or target registers may be used.  The following

 * mmio_config_* accessors enforce this.  See "BIOS and Kernel Developer's

 * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1,

 * "MMIO Configuration Coding Requirements".

 */

static inline unsigned char mmio_config_readb(void __iomem *pos)

{