Merge "msm: npu: Add ssr support in dsp mode" (213a3c20) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/media/platform/msm/npu/npu_common.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -240,6 +240,6 @@ int npu_set_uc_power_level(struct npu_device *npu_dev,
		uint32_t pwr_level);

		int fw_init(struct npu_device *npu_dev);
		void fw_deinit(struct npu_device *npu_dev, bool fw_alive, bool ssr);
		void fw_deinit(struct npu_device *npu_dev, bool ssr);

		#endif /* _NPU_COMMON_H */

drivers/media/platform/msm/npu/npu_debugfs.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -374,7 +374,7 @@ static ssize_t npu_debug_ctrl_write(struct file *file,
		pr_info("error in fw_init\n");
		} else if (strcmp(buf, "off") == 0) {
		pr_info("triggering fw_deinit\n");
		fw_deinit(npu_dev, true, false);
		fw_deinit(npu_dev, false);
		} else if (strcmp(buf, "ssr") == 0) {
		pr_info("trigger error irq\n");
		if (npu_enable_core_power(npu_dev))

drivers/media/platform/msm/npu/npu_firmware.h

+27 −1

Original line number	Diff line number	Diff line
		@@ -31,8 +31,10 @@
		#define REG_NPU_HOST_CTRL_VALUE NPU_GPR2
		/* Simulates an interrupt for FW->HOST, used for pre-silicon */
		#define REG_FW_TO_HOST_EVENT NPU_GPR3
		/* Read/Written by both host and dsp for sync between driver and dsp */
		#define REG_HOST_DSP_CTRL_STATUS NPU_GPR4
		/* Data value for debug */
		#define REG_NPU_FW_DEBUG_DATA NPU_GPR4
		#define REG_NPU_FW_DEBUG_DATA NPU_GPR13

		/* Started job count */
		#define REG_FW_JOB_CNT_START NPU_GPR14
		@@ -87,6 +89,30 @@
		#define HOST_CTRL_STATUS_FW_PAUSE_VAL \
		(1 << HOST_CTRL_STATUS_FW_PAUSE)


		/* NPU HOST DSP Control/Status Register */
		/* notification of power up */
		/* following bits are set by host and read by dsp */
		#define HOST_DSP_CTRL_STATUS_PWR_UP_BIT 0
		/* notification of power dwn */
		#define HOST_DSP_CTRL_STATUS_PWR_DWN_BIT 1
		/* following bits are set by dsp and read by host */
		/* notification of power up acknowlegement*/
		#define HOST_DSP_CTRL_STATUS_PWR_UP_ACK_BIT 4
		/* notification of power down acknowlegement*/
		#define HOST_DSP_CTRL_STATUS_PWR_DWN_ACK_BIT 5


		/* 32 bit values of the bit fields above */
		#define HOST_DSP_CTRL_STATUS_PWR_UP_VAL \
		(1 << HOST_DSP_CTRL_STATUS_PWR_UP_BIT)
		#define HOST_DSP_CTRL_STATUS_PWR_DWN_VAL \
		(1 << HOST_DSP_CTRL_STATUS_PWR_DWN_BIT)
		#define HOST_DSP_CTRL_STATUS_PWR_UP_ACK_VAL \
		(1 << HOST_DSP_CTRL_STATUS_PWR_UP_ACK_BIT)
		#define HOST_DSP_CTRL_STATUS_PWR_DWN_ACK_VAL \
		(1 << HOST_DSP_CTRL_STATUS_PWR_DWN_ACK_BIT)

		/* Queue table header definition */
		struct hfi_queue_tbl_header {
		uint32_t qtbl_version; /* queue table version number */

drivers/media/platform/msm/npu/npu_hw.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -23,6 +23,8 @@
		#define NPU_CACHE_ATTR_IDn(n) (0x00100800+0x4*(n))
		#define NPU_MASTERn_IPC_IRQ_IN_CTRL(n) (0x00101008+0x1000*(n))
		#define NPU_MASTER0_IPC_IRQ_IN_CTRL__IRQ_SOURCE_SELECT___S 4
		#define NPU_MASTERn_IPC_IRQ_OUT_CTRL(n) (0x00101004+0x1000*(n))
		#define NPU_MASTER0_IPC_IRQ_OUT_CTRL__IRQ_TYPE_PULSE 4
		#define NPU_GPR0 (0x00100100)
		#define NPU_MASTERn_ERROR_IRQ_STATUS(n) (0x00101010+0x1000*(n))
		#define NPU_MASTERn_ERROR_IRQ_INCLUDE(n) (0x00101014+0x1000*(n))
		@@ -40,6 +42,7 @@
		#define NPU_GPR2 (0x00100108)
		#define NPU_GPR3 (0x0010010C)
		#define NPU_GPR4 (0x00100110)
		#define NPU_GPR13 (0x00100134)
		#define NPU_GPR14 (0x00100138)
		#define NPU_GPR15 (0x0010013C)

drivers/media/platform/msm/npu/npu_hw_access.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -147,6 +147,13 @@ int32_t npu_interrupt_raise_m0(struct npu_device *npu_dev)
		return ret;
		}

		int32_t npu_interrupt_raise_dsp(struct npu_device *npu_dev)
		{
		npu_reg_write(npu_dev, NPU_MASTERn_IPC_IRQ_OUT_CTRL(1), 0x8);

		return 0;
		}

		/* -------------------------------------------------------------------------
		* Functions - ION Memory
		* -------------------------------------------------------------------------