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Commit 2120df47 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: enable virtual dce on SI 



Add the proper IP module when requested.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 07fecde5

drivers/gpu/drm/amd/amdgpu/si.c

+136 −4
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
#include "si_dma.h"

#include "dce_v6_0.h"

#include "si.h"

#include "dce_virtual.h"



static const u32 tahiti_golden_registers[] =

{
@@ -1897,6 +1898,74 @@ static const struct amdgpu_ip_block_version verde_ip_blocks[] = 
};





static const struct amdgpu_ip_block_version verde_ip_blocks_vd[] =

{

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &si_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 6,

		.minor = 0,

		.rev = 0,

		.funcs = &gmc_v6_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &si_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 6,

		.minor = 0,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 6,

		.minor = 0,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 6,

		.minor = 0,

		.rev = 0,

		.funcs = &gfx_v6_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &si_dma_ip_funcs,

	},

/*	{

		.type = AMD_IP_BLOCK_TYPE_UVD,

		.major = 3,

		.minor = 1,

		.rev = 0,

		.funcs = &si_null_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_VCE,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &si_null_ip_funcs,

	},

	*/

};



static const struct amdgpu_ip_block_version hainan_ip_blocks[] =

{

	{
@@ -1943,6 +2012,59 @@ static const struct amdgpu_ip_block_version hainan_ip_blocks[] = 
	},

};



static const struct amdgpu_ip_block_version hainan_ip_blocks_vd[] =

{

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &si_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 6,

		.minor = 0,

		.rev = 0,

		.funcs = &gmc_v6_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &si_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 6,

		.minor = 0,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 6,

		.minor = 0,

		.rev = 0,

		.funcs = &gfx_v6_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &si_dma_ip_funcs,

	},

};



int si_set_ip_blocks(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {
@@ -1950,12 +2072,22 @@ int si_set_ip_blocks(struct amdgpu_device *adev) 
	case CHIP_TAHITI:

	case CHIP_PITCAIRN:

	case CHIP_OLAND:

		if (adev->enable_virtual_display) {

			adev->ip_blocks = verde_ip_blocks_vd;

			adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks_vd);

		} else {

			adev->ip_blocks = verde_ip_blocks;

			adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks);

		}

		break;

	case CHIP_HAINAN:

		if (adev->enable_virtual_display) {

			adev->ip_blocks = hainan_ip_blocks_vd;

			adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks_vd);

		} else {

			adev->ip_blocks = hainan_ip_blocks;

			adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks);

		}

		break;

	default:

		BUG();