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Commit 20e338fa authored by Ashwini Muduganti's avatar Ashwini Muduganti Committed by Gerrit - the friendly Code Review server
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Revert "drm/msm/dsi-staging: Configure hz dependent settings for 7nm DSI PHY" 



This reverts commit 0f1620aa.

Change-Id: I9479e6ae941fb1531809c1a5a2efba56e11ec424
Signed-off-by: default avatarAshwini Muduganti <amudug@codeaurora.org>
parent 87e31886

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+2 −3
Original line number Diff line number Diff line
@@ -848,12 +848,12 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
	if (host_cfg->data_lanes & DSI_DATA_LANE_3)

		num_of_lanes++;



	if (config->bit_clk_rate_hz_override == 0) {

	if (config->bit_clk_rate_hz == 0) {

		h_period = DSI_H_TOTAL_DSC(timing);

		v_period = DSI_V_TOTAL(timing);

		bit_rate = h_period * v_period * timing->refresh_rate * bpp;

	} else {

		bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;

		bit_rate = config->bit_clk_rate_hz * num_of_lanes;

	}



	bit_rate_per_lane = bit_rate;
@@ -870,7 +870,6 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
	dsi_ctrl->clk_freq.byte_clk_rate = byte_clk_rate;

	dsi_ctrl->clk_freq.pix_clk_rate = pclk_rate;

	dsi_ctrl->clk_freq.esc_clk_rate = config->esc_clk_rate_hz;

	config->bit_clk_rate_hz = dsi_ctrl->clk_freq.byte_clk_rate * 8;



	rc = dsi_clk_set_link_frequencies(clk_handle, dsi_ctrl->clk_freq,

					dsi_ctrl->cell_index);

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+0 −2
Original line number Diff line number Diff line
@@ -503,7 +503,6 @@ struct dsi_cmd_engine_cfg { 
 * @cmd_engine:            Cmd engine configuration if panel is in cmd mode.

 * @esc_clk_rate_khz:      Esc clock frequency in Hz.

 * @bit_clk_rate_hz:       Bit clock frequency in Hz.

 * @bit_clk_rate_hz_override: DSI bit clk rate override from dt/sysfs.

 * @video_timing:          Video timing information of a frame.

 * @lane_map:              Mapping between logical and physical lanes.

 */
@@ -516,7 +515,6 @@ struct dsi_host_config { 
	} u;

	u64 esc_clk_rate_hz;

	u64 bit_clk_rate_hz;

	u64 bit_clk_rate_hz_override;

	struct dsi_mode_info video_timing;

	struct dsi_lane_map lane_map;

};

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+3 −4
Original line number Diff line number Diff line
@@ -4212,7 +4212,7 @@ static int dsi_display_request_update_dsi_bitrate(struct dsi_display *display, 
		return -EINVAL;

	}



	display->config.bit_clk_rate_hz_override = bit_clk_rate;

	display->config.bit_clk_rate_hz = bit_clk_rate;



	for (i = 0; i < display->ctrl_count; i++) {

		struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
@@ -4240,8 +4240,7 @@ static int dsi_display_request_update_dsi_bitrate(struct dsi_display *display, 
			goto error;

		}



		bit_rate = display->config.bit_clk_rate_hz_override *

						num_of_lanes;

		bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;

		bit_rate_per_lane = bit_rate;

		do_div(bit_rate_per_lane, num_of_lanes);

		pclk_rate = bit_rate;
@@ -4262,7 +4261,7 @@ static int dsi_display_request_update_dsi_bitrate(struct dsi_display *display, 
			goto error;

		}



		ctrl->host_config.bit_clk_rate_hz_override = bit_clk_rate;

		ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;

error:

		mutex_unlock(&ctrl->ctrl_lock);

drivers/gpu/drm/msm/dsi-staging/dsi_panel.c

+1 −1
Original line number Diff line number Diff line
@@ -3360,7 +3360,7 @@ int dsi_panel_get_host_cfg_for_mode(struct dsi_panel *panel, 
	config->video_timing.dsc_enabled = mode->priv_info->dsc_enabled;

	config->video_timing.dsc = &mode->priv_info->dsc;



	config->bit_clk_rate_hz_override = mode->priv_info->clk_rate_hz;

	config->bit_clk_rate_hz = mode->priv_info->clk_rate_hz;

	config->esc_clk_rate_hz = 19200000;

	mutex_unlock(&panel->panel_lock);

	return rc;

drivers/gpu/drm/msm/dsi-staging/dsi_phy.c

+0 −1
Original line number Diff line number Diff line
@@ -864,7 +864,6 @@ int dsi_phy_enable(struct msm_dsi_phy *phy, 
	phy->data_lanes = config->common_config.data_lanes;

	phy->dst_format = config->common_config.dst_format;

	phy->cfg.pll_source = pll_source;

	phy->cfg.bit_clk_rate_hz = config->bit_clk_rate_hz;



	/**

	 * If PHY timing parameters are not present in panel dtsi file,