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Commit 20b2656d authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/radeon: let's use GB for vm_size (v2) 



VM sizes smaller than 1GB doesn't make much sense anyway.

v2: fix typo and grammer

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e898c791

drivers/gpu/drm/radeon/radeon_device.c

+11 −11
Original line number Diff line number Diff line
@@ -1056,36 +1056,36 @@ static void radeon_check_arguments(struct radeon_device *rdev) 
	if (!radeon_check_pot_argument(radeon_vm_size)) {

		dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",

			 radeon_vm_size);

		radeon_vm_size = 4096;

		radeon_vm_size = 4;

	}



	if (radeon_vm_size < 4) {

		dev_warn(rdev->dev, "VM size (%d) to small, min is 4MB\n",

	if (radeon_vm_size < 1) {

		dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n",

			 radeon_vm_size);

		radeon_vm_size = 4096;

		radeon_vm_size = 4;

	}



       /*

        * Max GPUVM size for Cayman, SI and CI are 40 bits.

        */

	if (radeon_vm_size > 1024*1024) {

		dev_warn(rdev->dev, "VM size (%d) to large, max is 1TB\n",

	if (radeon_vm_size > 1024) {

		dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",

			 radeon_vm_size);

		radeon_vm_size = 4096;

		radeon_vm_size = 4;

	}



	/* defines number of bits in page table versus page directory,

	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the

	 * page table and the remaining bits are in the page directory */

	if (radeon_vm_block_size < 9) {

		dev_warn(rdev->dev, "VM page table size (%d) to small\n",

		dev_warn(rdev->dev, "VM page table size (%d) too small\n",

			 radeon_vm_block_size);

		radeon_vm_block_size = 9;

	}



	if (radeon_vm_block_size > 24 ||

	    radeon_vm_size < (1ull << radeon_vm_block_size)) {

		dev_warn(rdev->dev, "VM page table size (%d) to large\n",

	    (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {

		dev_warn(rdev->dev, "VM page table size (%d) too large\n",

			 radeon_vm_block_size);

		radeon_vm_block_size = 9;

	}
@@ -1238,7 +1238,7 @@ int radeon_device_init(struct radeon_device *rdev, 
	/* Adjust VM size here.

	 * Max GPUVM size for cayman+ is 40 bits.

	 */

	rdev->vm_manager.max_pfn = radeon_vm_size << 8;

	rdev->vm_manager.max_pfn = radeon_vm_size << 18;



	/* Set asic functions */

	r = radeon_asic_init(rdev);

drivers/gpu/drm/radeon/radeon_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -173,7 +173,7 @@ int radeon_dpm = -1; 
int radeon_aspm = -1;

int radeon_runtime_pm = -1;

int radeon_hard_reset = 0;

int radeon_vm_size = 4096;

int radeon_vm_size = 4;

int radeon_vm_block_size = 9;

int radeon_deep_color = 0;
@@ -243,7 +243,7 @@ module_param_named(runpm, radeon_runtime_pm, int, 0444); 
MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");

module_param_named(hard_reset, radeon_hard_reset, int, 0444);



MODULE_PARM_DESC(vm_size, "VM address space size in megabytes (default 4GB)");

MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");

module_param_named(vm_size, radeon_vm_size, int, 0444);



MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");