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Commit 20a440cc authored by Tony Truong's avatar Tony Truong
Browse files

ARM: dts: msm: disable L1/L1ss for PCIe on SM8150 



Disable L1 and L1ss for each PCIe core on SM8150 since the
link is not yet stable with it.

Change-Id: Ib27084f1cb5507a5fc73d94111f63edc009c45cd
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 5eadaf73

arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi

+0 −8
Original line number Diff line number Diff line
@@ -195,10 +195,6 @@ 
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;



		qcom,l1-supported;

		qcom,l1ss-supported;

		qcom,aux-clk-sync;



		qcom,max-link-speed = <0x3>;



		qcom,ep-latency = <10>;
@@ -485,10 +481,6 @@ 
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;



		qcom,l1-supported;

		qcom,l1ss-supported;

		qcom,aux-clk-sync;



		qcom,max-link-speed = <0x3>;



		qcom,ep-latency = <10>;