Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 20937056 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v4.9-tag3' of... 

Merge tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull renesas clk driver updates from Geert Uytterhoeven:

  - External crystal selection for RZ/A1,
  - CMT clocks for R-Car H3 and M3-W,
  - RAVB and Thermal clocks for R-Car M3-W.

* tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add CMT clocks
  clk: renesas: r8a7795: Add CMT clocks
  clk: renesas: r8a7796: Add RAVB clock
  clk: renesas: r8a7796: Add THS/TSC clock
  clk: renesas: rz: Select EXTAL vs USB clock
parents 8edeae56 5fad71f5

drivers/clk/renesas/clk-rz.c

+22 −2
Original line number Diff line number Diff line
@@ -25,10 +25,31 @@ struct rz_cpg { 
#define CPG_FRQCR	0x10

#define CPG_FRQCR2	0x14



#define PPR0		0xFCFE3200

#define PIBC0		0xFCFE7000



#define MD_CLK(x)	((x >> 2) & 1)	/* P0_2 */



/* -----------------------------------------------------------------------------

 * Initialization

 */



static u16 __init rz_cpg_read_mode_pins(void)

{

	void __iomem *ppr0, *pibc0;

	u16 modes;



	ppr0 = ioremap_nocache(PPR0, 2);

	pibc0 = ioremap_nocache(PIBC0, 2);

	BUG_ON(!ppr0 || !pibc0);

	iowrite16(4, pibc0);	/* enable input buffer */

	modes = ioread16(ppr0);

	iounmap(ppr0);

	iounmap(pibc0);



	return modes;

}



static struct clk * __init

rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)

{
@@ -37,8 +58,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na 
	static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };



	if (strcmp(name, "pll") == 0) {

		/* FIXME: cpg_mode should be read from GPIO. But no GPIO support yet */

		unsigned cpg_mode = 0; /* hardcoded to EXTAL for now */

		unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());

		const char *parent_name = of_clk_get_parent_name(np, cpg_mode);



		mult = cpg_mode ? (32 / 4) : 30;

drivers/clk/renesas/r8a7795-cpg-mssr.c

+4 −0
Original line number Diff line number Diff line
@@ -123,6 +123,10 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 
	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S3D1),

	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S3D1),

	DEF_MOD("sys-dmac0",		 219,	R8A7795_CLK_S3D1),

	DEF_MOD("cmt3",			 300,	R8A7795_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A7795_CLK_R),

	DEF_MOD("cmt1",			 302,	R8A7795_CLK_R),

	DEF_MOD("cmt0",			 303,	R8A7795_CLK_R),

	DEF_MOD("scif2",		 310,	R8A7795_CLK_S3D4),

	DEF_MOD("sdif3",		 311,	R8A7795_CLK_SD3),

	DEF_MOD("sdif2",		 312,	R8A7795_CLK_SD2),

drivers/clk/renesas/r8a7796-cpg-mssr.c

+6 −0
Original line number Diff line number Diff line
@@ -109,6 +109,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {

	DEF_MOD("cmt3",			 300,	R8A7796_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A7796_CLK_R),

	DEF_MOD("cmt1",			 302,	R8A7796_CLK_R),

	DEF_MOD("cmt0",			 303,	R8A7796_CLK_R),

	DEF_MOD("scif2",		 310,	R8A7796_CLK_S3D4),

	DEF_MOD("sdif3",		 311,	R8A7796_CLK_SD3),

	DEF_MOD("sdif2",		 312,	R8A7796_CLK_SD2),
@@ -116,6 +120,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("sdif0",		 314,	R8A7796_CLK_SD0),

	DEF_MOD("rwdt0",		 402,	R8A7796_CLK_R),

	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S3D1),

	DEF_MOD("thermal",		 522,	R8A7796_CLK_CP),

	DEF_MOD("etheravb",		 812,	R8A7796_CLK_S0D6),

	DEF_MOD("gpio7",		 905,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio6",		 906,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio5",		 907,	R8A7796_CLK_S3D4),