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Commit 2003c78b authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'juno-updates-4.13' of... 

Merge tag 'juno-updates-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64

ARMv8 Vexpress/Juno DT updates for v4.13

1. Adds support for Coresight CPU debug MMIO interface on all Juno variants.

2. Enables support for few SMMUs on Juno which were previously disabled
   waiting for IOMMU-backed DMA API support to be stabilised.

* tag 'juno-updates-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux

:
  arm64: dts: juno: enable some SMMUs
  arm64: dts: juno: add coresight CPU debug nodes

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents b69cfb5a 6806f2c7

arch/arm64/boot/dts/arm/juno-base.dtsi

+54 −4
Original line number Original line Diff line number Diff line
@@ -53,7 +53,6 @@ 
		#global-interrupts = <1>;

		#global-interrupts = <1>;

		dma-coherent;

		dma-coherent;

		power-domains = <&scpi_devpd 0>;

		power-domains = <&scpi_devpd 0>;

		status = "disabled";

	};

	};





	gic: interrupt-controller@2c010000 {

	gic: interrupt-controller@2c010000 {
@@ -202,6 +201,15 @@ 
		};

		};

	};

	};





	cpu_debug0: cpu_debug@22010000 {

		compatible = "arm,coresight-cpu-debug", "arm,primecell";

		reg = <0x0 0x22010000 0x0 0x1000>;



		clocks = <&soc_smc50mhz>;

		clock-names = "apb_pclk";

		power-domains = <&scpi_devpd 0>;

	};



	etm0: etm@22040000 {

	etm0: etm@22040000 {

		compatible = "arm,coresight-etm4x", "arm,primecell";

		compatible = "arm,coresight-etm4x", "arm,primecell";

		reg = <0 0x22040000 0 0x1000>;

		reg = <0 0x22040000 0 0x1000>;
@@ -252,6 +260,15 @@ 
		};

		};

	};

	};





	cpu_debug1: cpu_debug@22110000 {

		compatible = "arm,coresight-cpu-debug", "arm,primecell";

		reg = <0x0 0x22110000 0x0 0x1000>;



		clocks = <&soc_smc50mhz>;

		clock-names = "apb_pclk";

		power-domains = <&scpi_devpd 0>;

	};



	etm1: etm@22140000 {

	etm1: etm@22140000 {

		compatible = "arm,coresight-etm4x", "arm,primecell";

		compatible = "arm,coresight-etm4x", "arm,primecell";

		reg = <0 0x22140000 0 0x1000>;

		reg = <0 0x22140000 0 0x1000>;
@@ -266,6 +283,15 @@ 
		};

		};

	};

	};





	cpu_debug2: cpu_debug@23010000 {

		compatible = "arm,coresight-cpu-debug", "arm,primecell";

		reg = <0x0 0x23010000 0x0 0x1000>;



		clocks = <&soc_smc50mhz>;

		clock-names = "apb_pclk";

		power-domains = <&scpi_devpd 0>;

	};



	etm2: etm@23040000 {

	etm2: etm@23040000 {

		compatible = "arm,coresight-etm4x", "arm,primecell";

		compatible = "arm,coresight-etm4x", "arm,primecell";

		reg = <0 0x23040000 0 0x1000>;

		reg = <0 0x23040000 0 0x1000>;
@@ -330,6 +356,15 @@ 
		};

		};

	};

	};





	cpu_debug3: cpu_debug@23110000 {

		compatible = "arm,coresight-cpu-debug", "arm,primecell";

		reg = <0x0 0x23110000 0x0 0x1000>;



		clocks = <&soc_smc50mhz>;

		clock-names = "apb_pclk";

		power-domains = <&scpi_devpd 0>;

	};



	etm3: etm@23140000 {

	etm3: etm@23140000 {

		compatible = "arm,coresight-etm4x", "arm,primecell";

		compatible = "arm,coresight-etm4x", "arm,primecell";

		reg = <0 0x23140000 0 0x1000>;

		reg = <0 0x23140000 0 0x1000>;
@@ -344,6 +379,15 @@ 
		};

		};

	};

	};





	cpu_debug4: cpu_debug@23210000 {

		compatible = "arm,coresight-cpu-debug", "arm,primecell";

		reg = <0x0 0x23210000 0x0 0x1000>;



		clocks = <&soc_smc50mhz>;

		clock-names = "apb_pclk";

		power-domains = <&scpi_devpd 0>;

	};



	etm4: etm@23240000 {

	etm4: etm@23240000 {

		compatible = "arm,coresight-etm4x", "arm,primecell";

		compatible = "arm,coresight-etm4x", "arm,primecell";

		reg = <0 0x23240000 0 0x1000>;

		reg = <0 0x23240000 0 0x1000>;
@@ -358,6 +402,15 @@ 
		};

		};

	};

	};





	cpu_debug5: cpu_debug@23310000 {

		compatible = "arm,coresight-cpu-debug", "arm,primecell";

		reg = <0x0 0x23310000 0x0 0x1000>;



		clocks = <&soc_smc50mhz>;

		clock-names = "apb_pclk";

		power-domains = <&scpi_devpd 0>;

	};



	etm5: etm@23340000 {

	etm5: etm@23340000 {

		compatible = "arm,coresight-etm4x", "arm,primecell";

		compatible = "arm,coresight-etm4x", "arm,primecell";

		reg = <0 0x23340000 0 0x1000>;

		reg = <0 0x23340000 0 0x1000>;
@@ -546,7 +599,6 @@ 
			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;

		#iommu-cells = <1>;

		#global-interrupts = <1>;

		#global-interrupts = <1>;

		status = "disabled";

	};

	};





	smmu_hdlcd0: iommu@7fb20000 {

	smmu_hdlcd0: iommu@7fb20000 {
@@ -556,7 +608,6 @@ 
			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;

		#iommu-cells = <1>;

		#global-interrupts = <1>;

		#global-interrupts = <1>;

		status = "disabled";

	};

	};





	smmu_usb: iommu@7fb30000 {

	smmu_usb: iommu@7fb30000 {
@@ -567,7 +618,6 @@ 
		#iommu-cells = <1>;

		#iommu-cells = <1>;

		#global-interrupts = <1>;

		#global-interrupts = <1>;

		dma-coherent;

		dma-coherent;

		status = "disabled";

	};

	};





	dma@7ff00000 {

	dma@7ff00000 {

arch/arm64/boot/dts/arm/juno-r1.dts

+24 −0
Original line number Original line Diff line number Diff line
@@ -281,3 +281,27 @@ 
&stm_out_port {

&stm_out_port {

	remote-endpoint = <&csys1_funnel_in_port0>;

	remote-endpoint = <&csys1_funnel_in_port0>;

};

};



&cpu_debug0 {

	cpu = <&A57_0>;

};



&cpu_debug1 {

	cpu = <&A57_1>;

};



&cpu_debug2 {

	cpu = <&A53_0>;

};



&cpu_debug3 {

	cpu = <&A53_1>;

};



&cpu_debug4 {

	cpu = <&A53_2>;

};



&cpu_debug5 {

	cpu = <&A53_3>;

};

arch/arm64/boot/dts/arm/juno-r2.dts

+24 −0
Original line number Original line Diff line number Diff line
@@ -281,3 +281,27 @@ 
&stm_out_port {

&stm_out_port {

	remote-endpoint = <&csys1_funnel_in_port0>;

	remote-endpoint = <&csys1_funnel_in_port0>;

};

};



&cpu_debug0 {

	cpu = <&A72_0>;

};



&cpu_debug1 {

	cpu = <&A72_1>;

};



&cpu_debug2 {

	cpu = <&A53_0>;

};



&cpu_debug3 {

	cpu = <&A53_1>;

};



&cpu_debug4 {

	cpu = <&A53_2>;

};



&cpu_debug5 {

	cpu = <&A53_3>;

};

arch/arm64/boot/dts/arm/juno.dts

+24 −0
Original line number Original line Diff line number Diff line
@@ -268,3 +268,27 @@ 
		};

		};

	};

	};

};

};



&cpu_debug0 {

	cpu = <&A57_0>;

};



&cpu_debug1 {

	cpu = <&A57_1>;

};



&cpu_debug2 {

	cpu = <&A53_0>;

};



&cpu_debug3 {

	cpu = <&A53_1>;

};



&cpu_debug4 {

	cpu = <&A53_2>;

};



&cpu_debug5 {

	cpu = <&A53_3>;

};