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Commit 1ed79e16 authored by Blagovest Kolenichev's avatar Blagovest Kolenichev
Browse files

Merge android-4.14-p.90 (a5e7b251) into msm-4.14 



* refs/heads/tmp-a5e7b251:
  Linux 4.14.90
  bpf, arm: fix emit_ldx_r and emit_mov_i using TMP_REG_1
  rtc: snvs: Add timeouts to avoid kernel lockups
  nvmet-rdma: fix response use after free
  i2c: uniphier-f: fix violation of tLOW requirement for Fast-mode
  i2c: uniphier: fix violation of tLOW requirement for Fast-mode
  i2c: scmi: Fix probe error on devices with an empty SMB0001 ACPI device node
  i2c: axxia: properly handle master timeout
  mlxsw: spectrum_switchdev: Fix VLAN device deletion via ioctl
  vhost/vsock: fix reset orphans race with close timeout
  cifs: In Kconfig CONFIG_CIFS_POSIX needs depends on legacy (insecure cifs)
  drm/ast: Fix connector leak during driver unload
  ethernet: fman: fix wrong of_node_put() in probe function
  ARM: 8815/1: V7M: align v7m_dma_inv_range() with v7 counterpart
  ARM: 8814/1: mm: improve/fix ARM v7_dma_inv_range() unaligned address handling
  net/mlx4_en: Fix build break when CONFIG_INET is off
  mv88e6060: disable hardware level MAC learning
  libata: whitelist all SAMSUNG MZ7KM* solid-state disks
  Input: omap-keypad - fix keyboard debounce configuration
  Input: synaptics - enable SMBus for HP 15-ay000
  clk: mmp: Off by one in mmp_clk_add()
  clk: mvebu: Off by one bugs in cp110_of_clk_get()
  drm/msm: Fix error return checking
  ide: pmac: add of_node_put()
  drivers/tty: add missing of_node_put()
  drivers/sbus/char: add of_node_put()
  sbus: char: add of_node_put()
  SUNRPC: Fix a potential race in xprt_connect()
  nfs: don't dirty kernel pages read by direct-io
  bpf: Fix verifier log string check for bad alignment.
  bonding: fix 802.3ad state sent to partner when unbinding slave
  ARC: io.h: Implement reads{x}()/writes{x}()
  drm/msm: Grab a vblank reference when waiting for commit_done
  x86/earlyprintk/efi: Fix infinite loop on some screen widths
  scsi: vmw_pscsi: Rearrange code to avoid multiple calls to free_irq during unload
  scsi: libiscsi: Fix NULL pointer dereference in iscsi_eh_session_reset
  Input: hyper-v - fix wakeup from suspend-to-idle
  mac80211_hwsim: fix module init error paths for netlink
  locking/qspinlock: Fix build for anonymous union in older GCC compilers
  IB/hfi1: Remove race conditions in user_sdma send path
  mac80211: Fix condition validating WMM IE
  mac80211: don't WARN on bad WMM parameters from buggy APs
  netfilter: ipset: Fix wraparound in hash:*net* types
  elevator: lookup mq vs non-mq elevators
  locking/qspinlock, x86: Provide liveness guarantee
  locking/qspinlock/x86: Increase _Q_PENDING_LOOPS upper bound
  locking/qspinlock: Re-order code
  locking/qspinlock: Kill cmpxchg() loop when claiming lock from head of queue
  locking/qspinlock: Remove duplicate clear_pending() function from PV code
  locking/qspinlock: Remove unbounded cmpxchg() loop from locking slowpath
  locking/qspinlock: Merge 'struct __qspinlock' into 'struct qspinlock'
  locking/qspinlock: Bound spinning on pending->locked transition in slowpath
  locking/qspinlock: Ensure node is initialised before updating prev->next
  locking: Remove smp_read_barrier_depends() from queued_spin_lock_slowpath()
  x86/build: Fix compiler support check for CONFIG_RETPOLINE
  drm/amdgpu: update SMC firmware image for polaris10 variants
  drm/i915/execlists: Apply a full mb before execution for Braswell
  Revert "drm/rockchip: Allow driver to be shutdown on reboot/kexec"
  drm/nouveau/kms: Fix memory leak in nv50_mstm_del()
  powerpc/msi: Fix NULL pointer access in teardown code
  tracing: Fix memory leak of instance function hash filters
  tracing: Fix memory leak in set_trigger_filter()
  dm cache metadata: verify cache has blocks in blocks_are_clean_separate_dirty()
  dm thin: send event about thin-pool state change _after_ making it
  ARM: mmp/mmp2: fix cpu_is_mmp2() on mmp2-dt
  fuse: continue to send FUSE_RELEASEDIR when FUSE_OPEN returns ENOSYS
  mmc: sdhci: fix the timeout check window for clock and reset
  MMC: OMAP: fix broken MMC on OMAP15XX/OMAP5910/OMAP310
  arm64: dma-mapping: Fix FORCE_CONTIGUOUS buffer clearing
  userfaultfd: check VM_MAYWRITE was set after verifying the uffd is registered
  aio: fix spectre gadget in lookup_ioctx
  pinctrl: sunxi: a83t: Fix IRQ offset typo for PH11
  timer/debug: Change /proc/timer_list from 0444 to 0400

Change-Id: I9c3c7020caccfea06edafeb33c2740560bb6cc12
Signed-off-by: default avatarBlagovest Kolenichev <bkolenichev@codeaurora.org>
parents 0d58d668 a5e7b251

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 14

SUBLEVEL = 89

SUBLEVEL = 90

EXTRAVERSION =

NAME = Petit Gorille

arch/arc/include/asm/io.h

+72 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/types.h>

#include <asm/byteorder.h>

#include <asm/page.h>

#include <asm/unaligned.h>



#ifdef CONFIG_ISA_ARCV2

#include <asm/barrier.h>
@@ -94,6 +95,42 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) 
	return w;

}



/*

 * {read,write}s{b,w,l}() repeatedly access the same IO address in

 * native endianness in 8-, 16-, 32-bit chunks {into,from} memory,

 * @count times

 */

#define __raw_readsx(t,f) \

static inline void __raw_reads##f(const volatile void __iomem *addr,	\

				  void *ptr, unsigned int count)	\

{									\

	bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0;	\

	u##t *buf = ptr;						\

									\

	if (!count)							\

		return;							\

									\

	/* Some ARC CPU's don't support unaligned accesses */		\

	if (is_aligned) {						\

		do {							\

			u##t x = __raw_read##f(addr);			\

			*buf++ = x;					\

		} while (--count);					\

	} else {							\

		do {							\

			u##t x = __raw_read##f(addr);			\

			put_unaligned(x, buf++);			\

		} while (--count);					\

	}								\

}



#define __raw_readsb __raw_readsb

__raw_readsx(8, b)

#define __raw_readsw __raw_readsw

__raw_readsx(16, w)

#define __raw_readsl __raw_readsl

__raw_readsx(32, l)



#define __raw_writeb __raw_writeb

static inline void __raw_writeb(u8 b, volatile void __iomem *addr)

{
@@ -126,6 +163,35 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr) 


}



#define __raw_writesx(t,f)						\

static inline void __raw_writes##f(volatile void __iomem *addr, 	\

				   const void *ptr, unsigned int count)	\

{									\

	bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0;	\

	const u##t *buf = ptr;						\

									\

	if (!count)							\

		return;							\

									\

	/* Some ARC CPU's don't support unaligned accesses */		\

	if (is_aligned) {						\

		do {							\

			__raw_write##f(*buf++, addr);			\

		} while (--count);					\

	} else {							\

		do {							\

			__raw_write##f(get_unaligned(buf++), addr);	\

		} while (--count);					\

	}								\

}



#define __raw_writesb __raw_writesb

__raw_writesx(8, b)

#define __raw_writesw __raw_writesw

__raw_writesx(16, w)

#define __raw_writesl __raw_writesl

__raw_writesx(32, l)



/*

 * MMIO can also get buffered/optimized in micro-arch, so barriers needed

 * Based on ARM model for the typical use case
@@ -141,10 +207,16 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr) 
#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })

#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })

#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })

#define readsb(p,d,l)		({ __raw_readsb(p,d,l); __iormb(); })

#define readsw(p,d,l)		({ __raw_readsw(p,d,l); __iormb(); })

#define readsl(p,d,l)		({ __raw_readsl(p,d,l); __iormb(); })



#define writeb(v,c)		({ __iowmb(); writeb_relaxed(v,c); })

#define writew(v,c)		({ __iowmb(); writew_relaxed(v,c); })

#define writel(v,c)		({ __iowmb(); writel_relaxed(v,c); })

#define writesb(p,d,l)		({ __iowmb(); __raw_writesb(p,d,l); })

#define writesw(p,d,l)		({ __iowmb(); __raw_writesw(p,d,l); })

#define writesl(p,d,l)		({ __iowmb(); __raw_writesl(p,d,l); })



/*

 * Relaxed API for drivers which can handle barrier ordering themselves

arch/arm/mach-mmp/cputype.h

+4 −2
Original line number Diff line number Diff line
@@ -44,10 +44,12 @@ static inline int cpu_is_pxa910(void) 
#define cpu_is_pxa910()	(0)

#endif



#ifdef CONFIG_CPU_MMP2

#if defined(CONFIG_CPU_MMP2) || defined(CONFIG_MACH_MMP2_DT)

static inline int cpu_is_mmp2(void)

{

	return (((read_cpuid_id() >> 8) & 0xff) == 0x58);

	return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&

		(((mmp_chip_id & 0xfff) == 0x410) ||

		 ((mmp_chip_id & 0xfff) == 0x610));

}

#else

#define cpu_is_mmp2()	(0)

arch/arm/mm/cache-v7.S

+5 −3
Original line number Diff line number Diff line
@@ -359,14 +359,16 @@ ENTRY(v7_dma_inv_range) 
	ALT_UP(W(nop))

#endif

	mcrne	p15, 0, r0, c7, c14, 1		@ clean & invalidate D / U line

	addne	r0, r0, r2



	tst	r1, r3

	bic	r1, r1, r3

	mcrne	p15, 0, r1, c7, c14, 1		@ clean & invalidate D / U line

1:

	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D / U line

	add	r0, r0, r2

	cmp	r0, r1

1:

	mcrlo	p15, 0, r0, c7, c6, 1		@ invalidate D / U line

	addlo	r0, r0, r2

	cmplo	r0, r1

	blo	1b

	dsb	st

	ret	lr

arch/arm/mm/cache-v7m.S

+9 −5
Original line number Diff line number Diff line
@@ -73,9 +73,11 @@ 
/*

 * dcimvac: Invalidate data cache line by MVA to PoC

 */

.macro dcimvac, rt, tmp

	v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC

.irp    c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo

.macro dcimvac\c, rt, tmp

	v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC, \c

.endm

.endr



/*

 * dccmvau: Clean data cache line by MVA to PoU
@@ -369,14 +371,16 @@ v7m_dma_inv_range: 
	tst	r0, r3

	bic	r0, r0, r3

	dccimvacne r0, r3

	addne	r0, r0, r2

	subne	r3, r2, #1	@ restore r3, corrupted by v7m's dccimvac

	tst	r1, r3

	bic	r1, r1, r3

	dccimvacne r1, r3

1:

	dcimvac r0, r3

	add	r0, r0, r2

	cmp	r0, r1

1:

	dcimvaclo r0, r3

	addlo	r0, r0, r2

	cmplo	r0, r1

	blo	1b

	dsb	st

	ret	lr